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PNX8526
Programmable source decoder with integrated peripherals
Rev. 01 - 6 October 2003 Preliminary data
1. General description
The PNX8526 is a highly integrated media processor for use in Advanced Set Top Boxes (ASTB) and Digital Television (DTV) systems. The PNX8526 is targeted at the mid to high-end ASTB/DTV systems, decoding "all format" HD and SD MPEG2 source material with Standard Definition (SD), or double line-rate SD display capabilities. Although the PNX8526 can process high level input formats, its display capabilities are primarily targeted at NTSC, PAL and SECAM televisions. It is also intended for lower cost DTVs, those not considered high definition. Progressive output is also available for double line-rate television displays, or for high resolution graphic content to be displayed on a computer monitor. The PNX8526 is designed in a high performance 0.12-micron process. The PNX8526 performs source decode functions, including - conditional access, MPEG2 transport stream de-mux, MPEG2 video decode, audio decode and processing, graphics generation, video processing, and image composition and display. A 32-bit 200 MHz VLIW processor, referred to as the TriMediaTM 3200 CPU core (TM32 CPU), carries out the majority of media processing operations performed by the PNX8526. Fixed function hardware will perform some operations that are not handled by the TM32 CPU. Additionally, the PNX8526 supports a number of peripheral interfaces such as I2C, USB, IDE and UART. Other interfaces such as IEEE-1284 and Ethernet may be supported via Super I/O devices that reside on a PCI expansion bus. The expansion bus also provides for glueless interface to 8-bit wide slave devices, such as Flash/ROM, DOCSIS modem, UARTs, etc. An embedded MIPS processor (PR3940) running at 150 MHz is intended to run the OS. (There is no direct support for an external processor; however, a CPU of any type may be connected to the PNX8526 via the PCI interface.) This implies a complete CPU subsystem consisting of the CPU itself, local memory, and an interface to PCI. The MIPS processor is primarily responsible for control functions and graphics-intensive operating systems, while the TM32 CPU is responsible for running all real-time media processing functions. All resources supported within the PNX8526 are accessible by both the MIPS processor and the TM32 CPU. The software documentation of the PNX8526 provides more details on the interaction between the MIPS and the TM32 CPU. The PNX8526 is intended to be used with a small companion IC, the PNX8510. This analog companion chip provides the majority of analog video and audio support for the output of the PNX8526. The PNX8510 companion is capable of simultaneously driving two video channels (6 DACs) and two stereo audio channels (4 DACs).
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
2. Features
200 MHz, 5 instruction/clock cycle 32-bit VLIW processing core (TM32 CPU) 150 MHz, MIPS PR3940 processing core External CPU support via PCI Support for multiple digital video (D1) input streams Support for multiple MPEG2 or DIRECTV transport streams (parallel format) On-chip conditional access for DVB, DES, MULTI2, CAM, DIRECTV On-chip copy protection support for OpenCableTM and ATSC (NRSS-B) Simultaneous decode of two SD streams (MPEG2) or one HD MPEG Stream (AFD style HD-SD decode) Simultaneous decode of two AC-3 or equivalent audio streams High performance 2D rendering and DMA capability Dual image composition/screen refresh engines: four layer primary output, two layer secondary output Multiple channel output to support watch/record and multi-room modes Embedded 1394 link layer with 5C copy protection Soft modem support via SSI interface 16, 32, and 64 MB Unified Memory Architecture implemented with high speed SDRAM (166 MHz) System expansion capability via industry standard PCI bus Core peripherals (I2C, UART, USB, etc.) on the chip, other peripherals supported via third-party SuperIO chip
3. Applications
Advanced Set Top Box (ASTB) Digital Television (DTV)
4. Ordering information
Table 1: Ordering Information Description Version SOT610-1 Type number Package Name PNX8526EH
HBGA456 Plastic thermal enhanced ball grid array package; 456 balls; body 35 x 35 x 1.8 mm; heatsink
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
5. Block diagram
166 MHz, 64-bit wide SDRAM 1394 PHY
handbook, full pagewidth
1394 MMI TS_OUT* DV1 656* TS & 656 ROUTER 656 VIP1 AICP1 OUTPUT MODE VIP2 AICP2 AO1-3 DV_OUT1 656/HD/VGA DV_OUT2 656 I2S audio*
DV2 656/TS
656 TS
DV3 656/TS TS
MSP1-2
MSP3
SPDO
spdif audio
I2S audio*
AI1-3
TSDMA
spdif audio UART1-2* UART3/Sync Serial i/f* Gen. Purpose I/O USB host i/f (2 port) Smartcard1-2 I2S (2x) 12
SPDI
MBS
VMPG misc. I/O DE (2D)
27 MHz xtal
BOOT, RESET, CLOCK
JTAG
TM-DBG
DMA
TM32 MEDIA PROCESSOR 5 issue, 200 MHz 32 kB I$ 16 kB 2-port D$ 128 32-bit regs
PCI
PR3940 MIPS CPU 150 MHz 16 kB I$ 8 kB D$ R4K MMU
EJTAG debug
33 MHz, 32-bit PCI 2.2 (includes NAND/nor flash, IDE drive & 68k peripheral capability)
MCE540
I/O marked * can also function as general purpose serial I/O pins Due to pin sharing either AI3 or AO3 can be active, not both
Fig 1. PNX8526 - block diagram
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
6. Pinning information
MDB852
handbook,AF halfpage AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
PNX8526EH
ball A1 index area
1 2
3 4
5 6
7 8
9
11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
Fig 2. Pin configuration
6.1 Pinning
In the tables that follow the PNX8526 signals have been sorted by functional group. For quick reference, Table 2 identifies each functional group and gives table location.
Table 2: Functional Group PCI MISC MMI GPIO COM USB 1394 I2C-bus AVIF DVB PLL PWR TEST All pins Signal groups Group Name Peripheral Controller Interface Miscellaneous System Interface Main Memory Interface General Purpose Input/Output Serial Communication Universal Serial Bus IEEE 1394 Port Serial Communications Port Audio and Video Interface Digital Video Bus Phase Lock Loop Analog Power and Ground / Digital Power and Ground Connections Test Contacts Pin Descriptions in alpha/numeric order Table/Page Number Table 3 on page 5 Table 4 on page 7 Table 5 on page 7 Table 6 on page 9 Table 7 on page 10 Table 8 on page 10 Table 9 on page 11 Table 10 on page 11 Table 11 on page 11 Table 12 on page 13 Table 13 on page 14 Table 14 on page 14 Table 15 on page 17 Table 16 on page 18
6.2 Pin description
All pad inputs and I/O have built-in pull-ups (~80 k) and Schmitt trigger input thresholds. (See Table 19 for maximum ratings).
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
The following pins do not have pull-ups: XTALI, PCIx, analog pins, I2C, Main Memory Interface, USB_DPx and USB_DMx. The following pins do not have Schmitt trigger inputs: XTALI, analog pins, USB_DPx and USB_DMx.
Table 3: Peripheral Controller Interface (PCI) # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24] AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] AD[09] AD[08] AD[07] AD[06] AD[05] AD[04] AD[03] AD[02] AD[01] AD[00] C/BE[3] C/BE[2]
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Pin AB1 AB2 AB3 AB4 AC1 AC2 AC3 AD2 AE3 AF4 AE4 AD4 AE5 AD5 AC5 AC6 AD8 AC8 AF9 AE9 AD9 AC9 AF10 AE10 AC10 AF11 AE11 AD11 AC11 AE12 AD12 AC12 AD1 AF5
Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description Multiplexed Address or Data Bit 31 Multiplexed Address or Data Bit 30 Multiplexed Address or Data Bit 29 Multiplexed Address or Data Bit 28 Multiplexed Address or Data Bit 27 Multiplexed Address or Data Bit 26 Multiplexed Address or Data Bit 25 Multiplexed Address or Data Bit 24 Multiplexed Address or Data Bit 23 Multiplexed Address or Data Bit 22 Multiplexed Address or Data Bit 21 Multiplexed Address or Data Bit 20 Multiplexed Address or Data Bit 19 Multiplexed Address or Data Bit 18 Multiplexed Address or Data Bit 17 Multiplexed Address or Data Bit 16 Multiplexed Address or Data Bit 15 Multiplexed Address or Data Bit 14 Multiplexed Address or Data Bit 13 Multiplexed Address or Data Bit 12 Multiplexed Address or Data Bit 11 Multiplexed Address or Data Bit 10 Multiplexed Address or Data Bit 9 Multiplexed Address or Data Bit 8 Multiplexed Address or Data Bit 7 Multiplexed Address or Data Bit 6 Multiplexed Address or Data Bit 5 Multiplexed Address or Data Bit 4 Multiplexed Address or Data Bit 3 Multiplexed Address or Data Bit 2 Multiplexed Address or Data Bit 1 Multiplexed Address or Data Bit 0 Multiplexed Command or Byte Enable 3 Multiplexed Command or Byte Enable 2
Alternate Function
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 3: Peripheral Controller Interface (PCI)...continued # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol C/BE[1] C/BE[0] CLK DEVSEL FRAME GNT Pin AE8 AD10 AA1 AF7 AF6 Y3 Type I/O I/O I I/O I/O I/O Description Multiplexed Command or Byte Enable 1 Multiplexed Command or Byte Enable 0 PCI Bus Clock Device Select is asserted when a target address is decoded and remains asserted to indicate that a target device is selected. Frame is asserted to indicate start of bus transaction and remains asserted until final data phase begins. Arbitration Grant is asserted to indicate access to the bus has been granted. This pin is an input when an external arbiter is used and an output when using the internal arbiter. Auxiliary Arbitration Grant_A is asserted to indicate bus access has been granted to an external PCI master. Used where internal arbiter is configured. Auxiliary Arbitration Grant_B is asserted to indicate bus access has been granted to an external PCI master. Used where internal arbiter is configured. Initialization Device Select provides chip select during configuration read and write transactions. Interrupt A is asserted to request an interrupt. This pin may be configured as an input if the internal PIC is used, or as an output if the external interrupt controller is used. Polarity in active low. Initiator Ready is asserted during writes to indicate valid data on AD[31:0]. Also asserted during reads to indicate the target is prepared to accept data. Wait states are inserted until IRDY and TRDY are both asserted. Parity supports even parity across the PCI Address/Data Bus AD[31:0]) and Command/ Byte Enable Bus (C/BE[3:0]). The Bus Master drives PAR for address and write data phases. The Target drives PAR for the read data phases. Parity Error indicates data parity errors during all PCI transactions except Special Cycle. Arbitration Request on PCI Bus. Request is an output when using an external arbiter and an input when using an internal arbiter. Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where internal arbiter is configured. Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where internal arbiter is configured. PCI Bus Global Reset System Error Stop is asserted to indicate a request from the target for the master to stop the current transmission. Target Ready is asserted during reads to indicate valid data on AD[31:0]. It is asserted during writes to indicate the target is prepared to accept data. Wait states are inserted until IRDY and TRDY are both asserted. # # # Alternate Function
GNT_A
Y4
I/O
GNT_B
AA4
I/O
#
IDSEL INTA
AF3 V4
I/O I/O
IRDY
AE6
I/O
PAR
AF8
I/O
PERR REQ REQ_A REQ_B RESET_IN SERR STOP TRDY
AD7 Y2 AA2 AA3 W3 AC7 AE7 AD6
I/O I/O I/O I/O I I/O I/O I/O
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 4: Misc. System Interface (MISC) # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol XIO_A25 XIO_ACK XIO_SEL[2] XIO_SEL[1] XIO_SEL[0] SYS_RSTN_OUT Pin AE13 AF13 AF12 AC13 AD13 Y1 Type I/O I/O I/O I/O I/O O Description XIO Address Bit 25 XIO Acknowledge (EEPROM) External I/O Select2 External I/O Select1 External I/O Select0 System Reset Output Alternate Function # # # # # #
Table 5: Main Memory Interface (MMI) # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol MA[11] MA[10] MA[9] MA[8] MA[7] MA[6] MA[5] MA[4] MA[3] MA[2] MA[1] MA[0] MD[63] MD[62] MD[61] MD[60] MD[59] MD[58] MD[57] MD[56] MD[55] MD[54] MD[53] MD[52] MD[51] MD[50] MD[49] MD[48] MD[47]
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Pin C22 B21 A21 C21 A20 C20 D18 D19 C19 D20 B20 D21 M25 M24 M23 L26 L25 L24 L23 K26 K24 K23 J26 J25 J24 J23 H26 H25 H23
Type O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description Memory Address Bit 11 Memory Address Bit 10 Memory Address Bit 9 Memory Address Bit 8 Memory Address Bit 7 Memory Address Bit 6 Memory Address Bit 5 Memory Address Bit 4 Memory Address Bit 3 Memory Address Bit 2 Memory Address Bit 1 Memory Address Bit 0 Memory Data Bit 63 Memory Data Bit 62 Memory Data Bit 61 Memory Data Bit 60 Memory Data Bit 59 Memory Data Bit 58 Memory Data Bit 57 Memory Data Bit 56 Memory Data Bit 55 Memory Data Bit 54 Memory Data Bit 53 Memory Data Bit 52 Memory Data Bit 51 Memory Data Bit 50 Memory Data Bit 49 Memory Data Bit 48 Memory Data Bit 47
Alternate Function
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 5: Main Memory Interface (MMI)...continued # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol MD[46] MD[45] MD[44] MD[43] MD[42] MD[41] MD[40] MD[39] MD[38] MD[37] MD[36] MD[35] MD[34] MD[33] MD[32] MD[31] MD[30] MD[29] MD[28] MD[27] MD[26] MD[25] MD[24] MD[23] MD[22] MD[21] MD[20] MD[19] MD[18] MD[17] MD[16] MD[15] MD[14] MD[13] MD[12] MD[11] MD[10] MD[09] MD[08]
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Pin G26 G25 G24 G23 F26 F25 F24 F23 E25 E24 D25 D26 E23 D24 C25 A18 B18 C18 A19 B17 C17 D17 A16 B16 C16 D16 A15 B15 C15 D15 C14 A14 D14 A13 B13 C13 D13 A12 B12
Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description Memory Data Bit 46 Memory Data Bit 45 Memory Data Bit 44 Memory Data Bit 43 Memory Data Bit 42 Memory Data Bit 41 Memory Data Bit 40 Memory Data Bit 39 Memory Data Bit 38 Memory Data Bit 37 Memory Data Bit 36 Memory Data Bit 35 Memory Data Bit 34 Memory Data Bit 33 Memory Data Bit 32 Memory Data Bit 31 Memory Data Bit 30 Memory Data Bit 29 Memory Data Bit 28 Memory Data Bit 27 Memory Data Bit 26 Memory Data Bit 25 Memory Data Bit 24 Memory Data Bit 23 Memory Data Bit 22 Memory Data Bit 21 Memory Data Bit 20 Memory Data Bit 19 Memory Data Bit 18 Memory Data Bit 17 Memory Data Bit 16 Memory Data Bit 15 Memory Data Bit 14 Memory Data Bit 13 Memory Data Bit 12 Memory Data Bit 11 Memory Data Bit 10 Memory Data Bit 09 Memory Data Bit 08
Alternate Function
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 5: Main Memory Interface (MMI)...continued # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol MD[07] MD[06] MD[05] MD[04] MD[03] MD[02] MD[01] MD[00] MDQM[7] MDQM[6] MDQM[5] MDQM[4] MDQM[3] MDQM[2] MDQM[1] MDQM[0] MBA[1] MBA[0] MCKE MCLK[1] MCLK[0] MCS MRAS MCAS MWE Pin C12 A11 B11 D11 A10 C11 B10 C10 K25 H24 E26 A24 A17 B14 D12 A9 D22 B22 C23 C26 B19 A22 B23 A23 B24 Type I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O Description Memory Data Bit 07 Memory Data Bit 06 Memory Data Bit 05 Memory Data Bit 04 Memory Data Bit 03 Memory Data Bit 02 Memory Data Bit 01 Memory Data Bit 00 SDRAM Control Bit 7 SDRAM Control Bit 6 SDRAM Control Bit 5 SDRAM Control Bit 4 SDRAM Control Bit 3 SDRAM Control Bit 2 SDRAM Control Bit 1 SDRAM Control Bit 0 SDRAM Bank Select SDRAM Bank Select Memory Clock Enable Memory Clock Memory Clock Memory Chip Select EDODRAM Row Address Strobe Memory Column Address Select Memory Write Enable Alternate Function
Table 6: General Purpose Input/Output (GPIO) # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol GPIO[11] GPIO[10] GPIO[9] GPIO[8] GPIO[7] GPIO[6] GPIO[5] GPIO[4] GPIO[3] Pin N26 N24 N23 M26 AE14 AF14 AD14 AC14 C5 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O Description General Purpose Input/Output Bit 11 General Purpose Input/Output Bit 10 General Purpose Input/Output Bit 9 General Purpose Input/Output Bit 8 General Purpose Input/Output Bit 7 General Purpose Input/Output Bit 6 General Purpose Input/Output Bit 5 General Purpose Input/Output Bit 4 General Purpose Input/Output Bit 3 Alternate Function # # # # # # # # #
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 6: General Purpose Input/Output (GPIO)...continued # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol GPIO[2] GPIO[1] GPIO[0] Pin B4 D5 C4 Type I/O I/O I/O Description General Purpose Input/Output Bit 2 General Purpose Input/Output Bit 1 General Purpose Input/Output Bit 0 Alternate Function # # #
Table 7: Serial Communication (COM) # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol UA1_TX UA1_RX UA2_TX UA2_RX UA2_RTSN UA2_CTSN SC1_DA SC1_CMD SC1_RST SC1_OFFN SC1_SCCK SC2_DA SC2_CMD SC2_RST SC2_OFFN SC2_SCCK SSI_SCLK_CTSN SSI_FS_RTSN SSI_RXD SSI_TXD Table 8: Symbol USB_DP[1] USB_DP[0] USB_DM[0] USB_DM[1] USB_PWR Pin U24 U25 T23 U26 T24 T25 T26 R23 R24 R25 R26 P23 P24 P26 P25 N25 V1 V2 U4 V3 Type I/O I/O I/O I/O I/O I/O I/O O O I O I/O O O I O I/O I/O I/O I/O Description UART1 Transmit UART1 Receive UART2 Transmit UART2 Receive UART2 Request To Send UART2 Clear To Send Smart Card1 Data Smart Card1 Command Smart Card1 Reset Smart Card1 Off Smart Card1 Bit Clock Smart Card2 Data Smart Card2 Command Smart Card2 Reset Smart Card2 Off Smart Card2 Bit Clock Synchronous Serial Interface Clock Input Synchronous Serial Interface Frame Sync Synchronous Serial Interface Receive Synchronous Serial Interface Transmit # # # # Alternate Function # # # # # #
Universal Serial Bus (USB) Pin A5 B6 C6 D7 W1 Type I/O I/O I/O I/O O Description Data Plus Bit 1 Data Plus Bit 0 Data Minus Bit 0 Data Minus Bit 1 USB port power On/Off 0 = Power on 1 = Power off
USB_OVRCUR
W2
I
Indicates over current being drawn by a USB device 0 = Over current detected 1 = No over current
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 9: Symbol PHY_D[7] PHY_D[6] PHY_D[5] PHY_D[4] PHY_D[3] PHY_D[2] PHY_D[1] PHY_D[0]
IEEE 1394 port Pin B9 D10 C9 A8 B8 D9 C8 A7 B7 C7 B5 A6 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I Description PHY Data Bit 7. Data is expected on pins 7:0 for 400 MB packets. PHY Data Bit 6. Data is expected on pins 7:0 for 400 MB packets. PHY Data Bit 5. Data is expected on pins 7:0 for 400 MB packets. PHY Data Bit 4. Data is expected on pins 7:0 for 400 MB packets. PHY Data Bit 3. Data is expected on pins 3:0 for 200 MB packets. PHY Data Bit 2. Data is expected on pins 3:0 for 200 MB packets. PHY Data Bit 1. Data is expected on pins 1:0 for 100 MB packets. PHY Data Bit 0. Data is expected on pins 1:0 for 100 MB packets. PHY Control Bit 1. Indicates the mode for data on the Din port. PHY Control Bit 0. Indicates the mode for data on the Din port. Used by the link to make bus requests and to access PHY registers. This is a serial bus. A train of pulses is sent on this signal. Signals which type of isolation mode is used at the PHY-Link interface. 0 = This is 1394-1995 Annex J type isolation. Enables differentiator circuitry. 1 = Direct connection or single capacitor isolation mode. This will disable the differentiator circuitry.
PHY_CTL[1] PHY_CTL[0] PHY_LREQ PHY_ISO_N
CLK_L1394 Table 10: Symbol I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA
D8
I
System clock. 49.152 MHz input
Serial communication port (I2C) Pin D6 A4 H1 K4 Type I/O I/O I/O I/O Description Serial Communications Port (I2C-bus) Clock Serial Communications Port (I2C-bus) Data Serial Communications Port (I2C-bus) Clock Serial Communications Port (I2C-bus) Data
Table 11: Audio and video interface # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol DV_OUT1[9] DV_OUT1[8] DV_OUT1[7] DV_OUT1[6] DV_OUT1[5] DV_OUT1[4] DV_OUT1[3] DV_OUT1[2] DV_OUT1[1] DV_OUT1[0] DV_OUT2[9] DV_OUT2[8] DV_OUT2[7]
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Pin M2 M1 N4 N3 N1 N2 P2 P1 P4 P3 R2 R4 R3
Type Description O O O O O O O O O O O O O Digital Video Output1, Bit 9 for primary display channel from AICP Digital Video Output1, Bit 8 for primary display channel from AICP Digital Video Output1, Bit 7 for primary display channel from AICP Digital Video Output1, Bit 6 for primary display channel from AICP Digital Video Output1, Bit 5 for primary display channel from AICP Digital Video Output1, Bit 4 for primary display channel from AICP Digital Video Output1, Bit 3 for primary display channel from AICP Digital Video Output1, Bit 2 for primary display channel from AICP Digital Video Output1, Bit 1 for primary display channel from AICP Digital Video Output1, Bit 0 for primary display channel from AICP Digital Video Output2, Bit 9 for secondary display channel from AICP Digital Video Output2, Bit 8 for secondary display channel from AICP Digital Video Output2, Bit 7 for secondary display channel from AICP
Alternate Function
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 11: Audio and video interface...continued # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol DV_OUT2[6] DV_OUT2[5] DV_OUT2[4] DV_OUT2[3] DV_OUT2[2] DV_OUT2[1] DV_OUT2[0] DV_CLK1 DV_CLK2 HSYNC VSYNC BLANK I2S_IN1_OSCLK I2S_IN1_SCK I2S_IN1_WS I2S_IN1_SD I2S_IN2_OSCLK I2S_IN2_SCK I2S_IN2_WS I2S_IN2_SD I2S_IO_OSCLK I2S_IO_SCK I2S_IO_WS I2S_IO_SD[3] I2S_IO_SD[2] I2S_IO_SD[1] I2S_IO_SD[0[ I2S_OUT1_OSCLK I2S_OUT1_SCK I2S_OUT1_WS I2S_OUT1_SD I2S_OUT2_OSCLK I2S_OUT2_SCK I2S_OUT2_WS I2S_OUT2_SD SPDIF_IN SPDIF_OUT Pin T1 T2 T3 U1 T4 U2 U3 M3 R1 L1 L2 M4 Type Description O O O O O O O O O O I/O O Digital Video Output2, Bit 6 for secondary display channel from AICP Digital Video Output2, Bit 5 for secondary display channel from AICP Digital Video Output2, Bit 4 for secondary display channel from AICP Digital Video Output2, Bit 3 for secondary display channel from AICP Digital Video Output2, Bit 2 for secondary display channel from AICP Digital Video Output2, Bit 1 for secondary display channel from AICP Digital Video Output2, Bit 0 for secondary display channel from AICP Digital Video Clock1 for primary display channel from AICP Digital Video Clock2 for secondary display channel from AICP Horizontal Sync for primary display Vertical Sync for primary display Blanking for primary display Audio IN1OverSample Clock Audio IN1 Serial Clock Audio IN1 Word Select Audio IN1 Data Audio IN2 OverSample Clock Audio IN2 Serial Clock Audio IN2 Word Select Audio IN2 Data Audio IN/OUT OverSample Clock Audio IN/OUT Serial Clock Audio IN/OUT Word Select Audio IN/OUT Data Bit 3 Audio IN/OUT Data Bit 2 Audio IN/OUT Data Bit 1 Audio IN/OUT Data Bit 0 Audio OUT1 OverSample Clock Audio OUT1 Serial Clock Audio OUT1 Word Select Audio OUT1 Data Audio OUT2OverSample Clock Audio OUT2 Serial Clock Audio OUT2 Word Select Audio OUT2 Data Multi-ch/SPDIF Input Multi-ch/SPDIF Output # # # # # # # # # # # Alternate Function
AD20 O AC19 I/O AF21 I/O AE21 I AD21 O AC20 I/O AF22 I/O AE22 I AF15 I/O AE15 I/O AC15 I/O AD15 I/O AF16 I/O AE16 I/O AD16 I/O K3 J1 J3 J2 K2 L3 K1 L4 O I/O I/O O O I/O I/O O
AF17 I AC16 O
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 12: Digital video bus # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol DV1_DATA[9] DV1_DATA[8] DV1_DATA[7] DV1_DATA[6] DV1_DATA[5] DV1_DATA[4] DV1_DATA[3] DV1_DATA[2] DV1_DATA[1] DV1_DATA[0] DV1_VALID DV1_CLK DV2_DATA[7] DV2_DATA[6] DV2_DATA[5] DV2_DATA[4] DV2_DATA[3] DV2_DATA[2] DV2_DATA[1] DV2_DATA[0] DV2_SOP DV2_ERR DV2_VALID DV2_CLK DV3_DATA[7] DV3_DATA[6] DV3_DATA[5] DV3_DATA[4] DV3_DATA[3] DV3_DATA[2] DV3_DATA[1] DV3_DATA[0] DV3_SOP DV3_ERR DV3_VALID DV3_CLK TS_DATA[7] TS_DATA[6] TS_DATA[5]
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Pin AE17 AD17 AF18 AC17 AE18 AD18 AF19 AE19 AC18 AD19 AF20 AE20 AF23 AC21 AD22 AE23 AC22 AD23 AE24 AF24 AD24 AD26 AD25 AC24 W23 Y24 Y25 Y26 W24 V23 W25 W26 V24 U23 V25 V26 AB23 AC25 AB24
Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I I I I I I I I I/O I/O I/O
Description ITU-656 VIP Data Bit 9 (Most Significant Bit) ITU-656 VIP Data Bit 8 ITU-656 VIP Data Bit 7 ITU-656 VIP Data Bit 6 ITU-656 VIP Data Bit 5 ITU-656 VIP Data Bit 4 ITU-656 VIP Data Bit 3 ITU-656 VIP Data Bit 2 ITU-656 VIP Data Bit 1 ITU-656 VIP Data Bit 0 (Least Significant Bit) ITU-656 VIP Data Valid ITU-656 VIP Data Clock Digital Video Transport Stream2 Data Bit 7 Digital Video Transport Stream2 Data Bit 6 Digital Video Transport Stream2 Data Bit 5 Digital Video Transport Stream2 Data Bit 4 Digital Video Transport Stream2 Data Bit 3 Digital Video Transport Stream2 Data Bit 2 Digital Video Transport Stream2 Data Bit 1 Digital Video Transport Stream2 Data Bit 0 Digital Video Transport Stream2 Start of Packet Digital Video Transport Stream2 Error Digital Video Transport Stream2 Data Valid Digital Video Transport Stream2 Clock Digital Video Transport Stream3 Data Bit 7 Digital Video Transport Stream3 Data Bit 6 Digital Video Transport Stream3 Data Bit 5 Digital Video Transport Stream3 Data Bit 4 Digital Video Transport Stream3 Data Bit 3 Digital Video Transport Stream3 Data Bit 2 Digital Video Transport Stream3 Data Bit 1 Digital Video Transport Stream3 Data Bit 0 Digital Video Transport Stream3 Start of Packet Digital Video Transport Stream3 Error Digital Video Transport Stream3 Data Valid Digital Video Transport Stream3 Clock Transport Stream Data Bit 7 Transport Stream Data Bit 6 Transport Stream Data Bit 5
Alternate Function # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 12: Digital video bus...continued # indicates multiplexed signal, see Section 6.2.1 for more details. Symbol TS_DATA[4] TS_DATA[3] TS_DATA[2] TS_DATA[1] TS_DATA[0] TS_SOP TS_VALID TS_CLK Pin AA23 AC26 AB25 AB26 Y23 AA24 AA25 AA26 Type I/O I/O I/O I/O I/O I/O I/O I/O Table 13: Symbol XTALI XTALO PLL_OUT Table 14: Symbol VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1
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Description Transport Stream Data Bit 4 Transport Stream Data Bit 3 Transport Stream Data Bit 2 Transport Stream Data Bit 1 Transport Stream Data Bit 0 Transport Stream Start of Packet (Parallel/Serial) Transport Stream Data Valid (Parallel/Serial) Transport Stream Clock (Parallel/Serial) Phase Lock Loop (PLL) Pin C2 D3 W4 Type Description I O O PLL Reference Crystal Input PLL Reference Crystal Feedback Driver General Purpose PLL Clock Output
Alternate Function # # # # # # # #
Analog and digital power (PWR) Pin AB18 AB17 AB14 AB13 AB12 AB9 AB8 N5 P5 U5 V5 K5 J5 E14 E13 E10 E9 E15 E18 E19 U22 V22 P22 Description System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 - 6 October 2003
14 of 59
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Analog and digital power (PWR)...continued Pin N22 K22 J22 D1 E2 E1 G4 F3 F2 F1 H4 G3 E4 E3 D2 F4 AB6 AB7 AB10 AB11 AB16 AB19 AB20 E12 E11 E8 E7 E16 E17 E20 E21 M22 L22 H22 G22 R22 T22 W22 Y22 T5 R5 Description System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts (Analog Power 1.728 GHz PLL) System 1.26 Volts (Analog Power 1.728 GHz PLL) System Ground (Analog Ground 1.728 GHz PLL) System Ground (Analog Ground 1.728 GHz PLL) System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 14: Symbol VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC1 VDDC2 VDDC2 VSS VSS VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Analog and digital power (PWR)...continued Pin M5 L5 W5 Y5 G5 H5 AB15 AF25 AF26 AE26 AE25 AC23 AB22 AB21 AA22 F22 E22 D23 C24 B25 A25 A26 B26 L15 L14 L13 L12 L11 M11 N11 P11 R11 T11 T12 T13 R13 R14 T14 T15 T16 R16 Description System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts System 3.3 Volts (CAB) System 3.3 Volts (CAB) System 3.3 Volts (TM-PLL) System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 14: Symbol VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Analog and digital power (PWR)...continued Pin AA5 AB5 AC4 AD3 AE2 AE1 AF1 AF2 F5 E5 E6 D4 B2 A2 A1 B1 R15 R12 P12 P13 N13 N14 P14 P15 P16 N16 N15 N12 M12 M13 M14 L16 M16 M15 Test Pin A3 B3 C3 C1 Type Description I O I I PR3940 Debug Port Data In PR3940 Debug Port Data Out PR3940 Debug Port Clock PR3940 Debug Port Mode Select
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 14: Symbol VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Table 15: Symbol DBG_TDI DBG_TDO DBG_TCK DBG_TMS
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Description System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground System Ground
Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Test...continued Pin J4 H2 G1 H3 Type Description I I O I I JTAG Port Reset JTAG Data IN JTAG Data OUT JTAG Data Clock JTAG Data Mode Select
Table 15: Symbol JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS Table 16: Symbol VSS VSS DBG_TDI I2C_SDA USB_DP[1] PHY_ISO_N All pins Pin A1 A2 A3 A4 A5 A6 Group PWR PWR TEST I2C-bus USB 1394
JTAG_TRST G2
Type I I/O I/O I
Description System Ground System Ground PR3940 Debug Port Data In Serial Communications Port (I2C-bus) Data Data Plus Bit 1 Signals type of isolation mode used at the PHY-Link interface. 0 = 1394-1995 Annex J type isolation. Enables differentiator circuitry. 1 = Direct connection or single capacitor isolation mode. This will disable the differentiator circuitry.
PHY_D[0] PHY_D[4] MDQM[0] MD[03] MD[06] MD[09] MD[13] MD[15] MD[20] MD[24] MDQM[3] MD[31] MD[28] MA[7] MA[9] MCS MCAS MDQM[4] VSS VSS VSS VSS DBG_TDO GPIO[2]
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A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4
1394 1394 MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI PWR PWR PWR PWR TEST GPIO
I/O I/O O I/O I/O I/O I/O I/O I/O I/O O I/O I/O O O O O O O I/O
PHY Data Bit 0. Data is expected on pins 1:0 for 100 MB packets. PHY Data Bit 4. Data is expected on pins 7:0 for 400 MB packets. SDRAM Control Bit 0 Memory Data Bit 03 Memory Data Bit 06 Memory Data Bit 09 Memory Data Bit 13 Memory Data Bit 15 Memory Data Bit 20 Memory Data Bit 24 SDRAM Control Bit 3 Memory Data Bit 31 Memory Data Bit 28 Memory Address Bit 7 Memory Address Bit 9 Memory Chip Select Memory Column Address Select SDRAM Control Bit 4 System Ground System Ground System Ground System Ground PR3940 Debug Port Data Out General Purpose Input/Output Bit 2
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol
All pins...continued Pin B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Group 1394 USB 1394 1394 1394 MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI PWR PWR TEST PLL TEST GPIO GPIO USB 1394 1394 1394 MMI MMI MMI MMI MMI MMI MMI MMI MMI Type O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O O O O O O O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Used by the link to make bus requests and to access PHY registers. This is a serial bus. A train of pulses is sent on this signal. Data Plus Bit 0 PHY Control Bit 1. Indicates the mode for data on the Din port. PHY Data Bit 3. Data is expected on pins 3:0 for 200 MB packets. PHY Data Bit 7. Data is expected on pins 7:0 for 400 MB packets. Memory Data Bit 01 Memory Data Bit 05 Memory Data Bit 08 Memory Data Bit 12 SDRAM Control Bit 2 Memory Data Bit 19 Memory Data Bit 23 Memory Data Bit 27 Memory Data Bit 30 Memory Clock Memory Address Bit 1 Memory Address Bit 10 SDRAM Bank Select EDODRAM Row Address Strobe Memory Write Enable System Ground System Ground PR3940 Debug Port Mode Select PLL Reference Crystal Input PR3940 Debug Port Clock General Purpose Input/Output Bit 0 General Purpose Input/Output Bit 3 Data Minus Bit 0 PHY Control Bit 0. Indicates the mode for data on the Din port. PHY Data Bit 1. Data is expected on pins 1:0 for 100 MB packets. PHY Data Bit 5. Data is expected on pins 7:0 for 400 MB packets. Memory Data Bit 00 Memory Data Bit 02 Memory Data Bit 07 Memory Data Bit 11 Memory Data Bit 16 Memory Data Bit 18 Memory Data Bit 22 Memory Data Bit 26 Memory Data Bit 29
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
PHY_LREQ USB_DP[0] PHY_CTL[1] PHY_D[3] PHY_D[7] MD[01] MD[05] MD[08] MD[12] MDQM[2] MD[19] MD[23] MD[27] MD[30] MCLK[0] MA[1] MA[10] MBA[0] MRAS MWE VSS VSS DBG_TMS XTALI DBG_TCK GPIO[0] GPIO[3] USB_DM[0] PHY_CTL[0] PHY_D[1] PHY_D[5] MD[00] MD[02] MD[07] MD[11] MD[16] MD[18] MD[22] MD[26] MD[29]
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol MA[3] MA[6] MA[8] MA[11] MCKE VSS MD[32] MCLK[1] VDDC VSS XTALO VSS GPIO[1] I2C_SCL
All pins...continued Pin C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 Group MMI MMI MMI MMI MMI PWR MMI MMI PWR PWR PLL PWR GPIO I2C-bus USB 1394 1394 1394 MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI MMI PWR MMI MMI MMI PWR PWR PWR PWR PWR PWR PWR Type O O O O O I/O O O I/O I/O I/O I I/O I/O I/O O I/O I/O I/O I/O I/O O O O O O I/O I/O I/O Description Memory Address Bit 3 Memory Address Bit 6 Memory Address Bit 8 Memory Address Bit 11 Memory Clock Enable System Ground Memory Data Bit 32 Memory Clock System 1.26 Volts System Ground (Analog Ground 1.728 GHz PLL) PLL Reference Crystal Feedback Driver System Ground General Purpose Input/Output Bit 1 Serial Communications Port (I2C-bus) Clock Data Minus Bit 1 System clock. 49.152 MHz input PHY Data Bit 2. Data is expected on pins 3:0 for 200 MB packets. PHY Data Bit 6. Data is expected on pins 7:0 for 400 MB packets. Memory Data Bit 04 SDRAM Control Bit 1 Memory Data Bit 10 Memory Data Bit 14 Memory Data Bit 17 Memory Data Bit 21 Memory Data Bit 25 Memory Address Bit 5 Memory Address Bit 4 Memory Address Bit 2 Memory Address Bit 0 SDRAM Bank Select System Ground Memory Data Bit 33 Memory Data Bit 36 Memory Data Bit 35 System 1.26 Volts System 1.26 Volts System 1.26 Volts (Analog Power 1.728 GHz PLL) System 1.26 Volts (Analog Power 1.728 GHz PLL) System Ground System Ground System 3.3 Volts
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
USB_DM[1] CLK_L1394 PHY_D[2] PHY_D[6] MD[04] MDQM[1] MD[10] MD[14] MD[17] MD[21] MD[25] MA[5] MA[4] MA[2] MA[0] MBA[1] VSS MD[33] MD[36] MD[35] VDDC1 VDDC1 VDDC2 VDDC2 VSS VSS VDD1
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol VDD1 VDDC1 VDDC1 VDD1 VDD1 VDDC1 VDDC1 VDDC1 VDD1 VDD1 VDDC1 VDDC1 VDD1 VDD1 VSS MD[34] MD[37] MD[38] MDQM[5] VDDC1 VDDC1 VDDC1 VSS VSS VSS MD[39] MD[40] MD[41] MD[42] JTAG_TCK
All pins...continued Pin E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 Group PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR MMI MMI MMI MMI PWR PWR PWR PWR PWR PWR MMI MMI MMI MMI TEST TEST PWR PWR PWR PWR MMI MMI MMI MMI TEST Type I/O I/O I/O O I/O I/O I/O I/O I I I/O I/O I/O I/O O Description System 3.3 Volts System 1.26 Volts System 1.26 Volts System 3.3 Volts System 3.3 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 3.3 Volts System 3.3 Volts System 1.26 Volts System 1.26 Volts System 3.3 Volts System 3.3 Volts System Ground Memory Data Bit 34 Memory Data Bit 37 Memory Data Bit 38 SDRAM Control Bit 5 System 1.26 Volts System 1.26 Volts System 1.26 Volts System Ground (Analog Ground 1.728 GHz PLL) System Ground System Ground Memory Data Bit 39 Memory Data Bit 40 Memory Data Bit 41 Memory Data Bit 42 JTAG Data Clock JTAG Port Reset System 1.26 Volts System 1.26 Volts System 3.3 Volts (CAB) System 3.3 Volts Memory Data Bit 43 Memory Data Bit 44 Memory Data Bit 45 Memory Data Bit 46 Serial Communications Port (I2C-bus) Clock JTAG Data OUT
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
JTAG_TRST VDDC1 VDDC1 VDD2 VDD1 MD[43] MD[44] MD[45] MD[46] I2C2_SCL JTAG_TDO
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I2C-bus I/O
Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol JTAG_TMS VDDC1 VDD2 VDD1 MD[47] MDQM[6] MD[48] MD[49]
All pins...continued Pin H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 Group TEST PWR PWR PWR MMI MMI MMI MMI AVIF AVIF AVIF TEST PWR PWR MMI MMI MMI MMI AVIF AVIF AVIF I2C-bus PWR PWR MMI MMI MMI MMI AVIF AVIF AVIF AVIF PWR PWR PWR PWR PWR PWR PWR PWR MMI Type I I/O O I/O I/O I/O O I/O I I/O I/O I/O I/O I/O O O I/O I/O I/O O I/O O I/O I/O O I/O Description JTAG Data Mode Select System 1.26 Volts System 3.3 Volts (CAB) System 3.3 Volts Memory Data Bit 47 SDRAM Control Bit 6 Memory Data Bit 48 Memory Data Bit 49 Audio OUT1 Serial Clock Audio OUT1 Data Audio OUT1 Word Select JTAG Data IN System 1.26 Volts System 1.26 Volts Memory Data Bit 50 Memory Data Bit 51 Memory Data Bit 52 Memory Data Bit 53 Audio OUT2 Word Select Audio OUT2 OverSample Clock Audio OUT1 OverSample Clock Serial Communications Port (I2C-bus) Data System 1.26 Volts System 1.26 Volts Memory Data Bit 54 Memory Data Bit 55 SDRAM Control Bit 7 Memory Data Bit 56 Horizontal Sync for primary display Vertical Sync for primary display Audio OUT2 Serial Clock Audio OUT2 Data System 3.3 Volts System Ground System Ground System Ground System Ground System Ground System Ground System 3.3 Volts Memory Data Bit 57
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
I2S_OUT1_SCK I2S_OUT1_SD I2S_OUT1_WS JTAG_TDI VDDC1 VDDC1 MD[50] MD[51] MD[52] MD[53] I2S_OUT2_WS I2S_OUT2_OSCLK I2S_OUT1_OSCLK I2C2_SDA VDDC1 VDDC1 MD[54] MD[55] MDQM[7] MD[56] HSYNC VSYNC I2S_OUT2_SCK I2S_OUT2_SD VDD1 VSS VSS VSS VSS VSS VSS VDD1 MD[57]
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Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol MD[58] MD[59] MD[60]
All pins...continued Pin L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 Group MMI MMI MMI AVIF AVIF AVIF AVIF PWR PWR PWR PWR PWR PWR PWR PWR MMI MMI MMI GPIO AVIF AVIF AVIF AVIF PWR PWR PWR PWR PWR PWR PWR PWR GPIO GPIO COM GPIO AVIF AVIF AVIF AVIF PWR PWR Type I/O I/O I/O O O O O I/O I/O I/O I/O O O O O I/O I/O O I/O O O O O Description Memory Data Bit 58 Memory Data Bit 59 Memory Data Bit 60 Digital Video Output1, Bit 8 for primary display channel from AICP Digital Video Output1, Bit 9 for primary display channel from AICP Digital Video Clock1 for primary display channel from AICP Blanking for primary display System 3.3 Volts System Ground System Ground System Ground System Ground System Ground System Ground System 3.3 Volts Memory Data Bit 61 Memory Data Bit 62 Memory Data Bit 63 General Purpose Input/Output Bit 8 Digital Video Output1, Bit 5 for primary display channel from AICP Digital Video Output1, Bit 4 for primary display channel from AICP Digital Video Output1, Bit 6 for primary display channel from AICP Digital Video Output1, Bit 7 for primary display channel from AICP System 1.26 Volts System Ground System Ground System Ground System Ground System Ground System Ground System 1.26 Volts General Purpose Input/Output Bit 9 General Purpose Input/Output Bit 10 Smart Card2 Bit Clock General Purpose Input/Output Bit 11 Digital Video Output1, Bit 2 for primary display channel from AICP Digital Video Output1, Bit 3 for primary display channel from AICP Digital Video Output1, Bit 0 for primary display channel from AICP Digital Video Output1, Bit 1 for primary display channel from AICP System 1.26 Volts System Ground
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
DV_OUT1[8] DV_OUT1[9] DV_CLK1 BLANK VDD1 VSS VSS VSS VSS VSS VSS VDD1 MD[61] MD[62] MD[63] GPIO[8] DV_OUT1[5] DV_OUT1[4] DV_OUT1[6] DV_OUT1[7] VDDC1 VSS VSS VSS VSS VSS VSS VDDC1 GPIO[9] GPIO[10] SC2_SCCK GPIO[11] DV_OUT1[2] DV_OUT1[3] DV_OUT1[0] DV_OUT1[1] VDDC1 VSS
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol VSS VSS VSS VSS VSS VDDC1 SC2_DA SC2_CMD
All pins...continued Pin P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 Group PWR PWR PWR PWR PWR PWR COM COM COM COM AVIF AVIF AVIF AVIF PWR PWR PWR PWR PWR PWR PWR PWR COM COM COM COM AVIF AVIF AVIF AVIF PWR PWR PWR PWR PWR PWR PWR PWR COM COM COM Type I/O O I O O O O O O O I O O O O O I/O I/O I/O Description System Ground System Ground System Ground System Ground System Ground System 1.26 Volts Smart Card2 Data Smart Card2 Command Smart Card2 Off Smart Card2 Reset Digital Video Clock2 for secondary display channel from AICP Digital Video Output2, Bit 9 for secondary display channel from AICP Digital Video Output2, Bit 7 for secondary display channel from AICP Digital Video Output2, Bit 8 for secondary display channel from AICP System 3.3 Volts System Ground System Ground System Ground System Ground System Ground System Ground System 3.3 Volts Smart Card1 Command Smart Card1 Reset Smart Card1 Off Smart Card1 Bit Clock Digital Video Output2, Bit 6 for secondary display channel from AICP Digital Video Output2, Bit 5 for secondary display channel from AICP Digital Video Output2, Bit 4 for secondary display channel from AICP Digital Video Output2, Bit 2 for secondary display channel from AICP System 3.3 Volts System Ground System Ground System Ground System Ground System Ground System Ground System 3.3 Volts UART2 Transmit UART2 Request To Send UART2 Clear To Send
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC2_OFFN SC2_RST DV_CLK2 DV_OUT2[9] DV_OUT2[7] DV_OUT2[8] VDD1 VSS VSS VSS VSS VSS VSS VDD1 SC1_CMD SC1_RST SC1_OFFN SC1_SCCK DV_OUT2[6] DV_OUT2[5] DV_OUT2[4] DV_OUT2[2] VDD1 VSS VSS VSS VSS VSS VSS VDD1 UA2_TX UA2_RTSN UA2_CTSN
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol SC1_DA
All pins...continued Pin T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 Group COM AVIF AVIF AVIF COM PWR PWR DVB COM COM COM COM COM COM PCI PWR PWR DVB DVB DVB DVB USB Type I/O O O O I/O I I/O I/O I/O I/O I/O I/O I/O I I I I O Description Smart Card1 Data Digital Video Output2, Bit 3 for secondary display channel from AICP Digital Video Output2, Bit 1 for secondary display channel from AICP Digital Video Output2, Bit 0 for secondary display channel from AICP Synchronous Serial Interface Receive System 1.26 Volts System 1.26 Volts Digital Video Transport Stream3 Error UART1 Transmit UART1 Receive UART2 Receive Synchronous Serial Interface CLock Synchronous Serial Interface Frame Sync Synchronous Serial Interface Transmit Interrupt Acknowledge is asserted to request an interrupt. System 1.26 Volts System 1.26 Volts Digital Video Transport Stream3 Data Bit 2 Digital Video Transport Stream3 Start of Packet Digital Video Transport Stream3 Data Valid Digital Video Transport Stream3 Clock USB port power On/Off 0 = Power on 1 = Power off
DV_OUT2[3] DV_OUT2[1] DV_OUT2[0] SSI_RXD VDDC1 VDDC1 DV3_ERR UA1_TX UA1_RX UA2_RX SSI_SCLK_CTSN SSI_FS_RTSN SSI_TXD INTA VDDC1 VDDC1 DV3_DATA[2] DV3_SOP DV3_VALID DV3_CLK USB_PWR
USB_OVRCUR
W2
USB
I
Indicates over current being drawn by a USB device: 0 = Over current detected 1 = No over current
RESET_IN PLL_OUT VDD1 VDD1 DV3_DATA[7] DV3_DATA[3] DV3_DATA[1] DV3_DATA[0] SYS_RSTN_OUT REQ GNT
W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3
PCI PLL PWR PWR DVB DVB DVB DVB MISC PCI PCI
I O I I I I O I/O I/O
PCI Bus Global Reset General Purpose PLL Clock Output System 3.3 Volts System 3.3 Volts Digital Video Transport Stream3 Data Bit 7 Digital Video Transport Stream3 Data Bit 3 Digital Video Transport Stream3 Data Bit 1 Digital Video Transport Stream3 Data Bit 0 System Reset Output Arbitration Request on PCI Bus. Request is an output when using an external arbiter and an input when using an internal arbiter. Arbitration Grant is asserted to indicate access to the bus has been granted. This pin is an input when an external arbiter is used and an output when using the internal arbiter.
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol GNT_A
All pins...continued Pin Y4 Group PCI Type I/O Description Auxiliary Arbitration Grant_A is asserted to indicate bus access has been granted to an external PCI master. Used where internal arbiter is configured. System 3.3 Volts System 3.3 Volts Transport Stream Data Bit 0 Digital Video Transport Stream3 Data Bit 6 Digital Video Transport Stream3 Data Bit 5 Digital Video Transport Stream3 Data Bit 4 PCI Bus Clock Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where internal arbiter is configured. Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where internal arbiter is configured. Auxiliary Arbitration Grant_B is asserted to indicate bus access has been granted to an external PCI master. Used where internal arbiter is configured. System Ground System Ground Transport Stream Data Bit 4 Transport Stream Start of Packet (Parallel/Serial) Transport Stream Data Valid (Parallel/Serial) Transport Stream Clock (Parallel/Serial) Multiplexed Address or Data Bit 31 Multiplexed Address or Data Bit 30 Multiplexed Address or Data Bit 29 Multiplexed Address or Data Bit 28 System Ground System 3.3 Volts System 3.3 Volts System 1.26 Volts System 1.26 Volts System 3.3 Volts System 3.3 Volts System 1.26 Volts System 1.26 Volts System 1.26 Volts System 3.3 Volts (TM-PLL) System 3.3 Volts System 1.26 Volts System 1.26 Volts
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
VDD1 VDD1 TS_DATA[0] DV3_DATA[6] DV3_DATA[5] DV3_DATA[4] CLK REQ_A
Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2
PWR PWR DVB DVB DVB DVB PCI PCI
I/O I I I I I/O
REQ_B
AA3
PCI
I/O
GNT_B
AA4
PCI
I/O
VSS VSS TS_DATA[4] TS_SOP TS_VALID TS_CLK AD[31] AD[30] AD[29] AD[28] VSS VDD1 VDD1 VDDC1 VDDC1 VDD1 VDD1 VDDC1 VDDC1 VDDC1 VDD1 VDD3 VDDC1 VDDC1
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AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18
PWR PWR DVB DVB DVB DVB PCI PCI PCI PCI PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR
I/O I/O I/O I/O I/O I/O I/O I/O -
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Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol VDD1 VDD1 VSS VSS
All pins...continued Pin AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 Group PWR PWR PWR PWR DVB DVB DVB DVB PCI PCI PCI PWR PCI PCI PCI PCI PCI PCI PCI PCI MISC GPIO AVIF AVIF DVB DVB AVIF AVIF DVB DVB PWR DVB DVB DVB PCI PCI PWR PCI PCI Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I I I I/O I/O I/O I/O I/O I/O Description System 3.3 Volts System 3.3 Volts System Ground System Ground Transport Stream Data Bit 7 Transport Stream Data Bit 5 Transport Stream Data Bit 2 Transport Stream Data Bit 1 Multiplexed Address or Data Bit 27 Multiplexed Address or Data Bit 26 Multiplexed Address or Data Bit 25 System Ground Multiplexed Address or Data Bit 17 Multiplexed Address or Data Bit 16 System Error Multiplexed Address or Data Bit 14 Multiplexed Address or Data Bit 10 Multiplexed Address or Data Bit 7 Multiplexed Address or Data Bit 3 Multiplexed Address or Data Bit 0 External I/O Select1 General Purpose Input/Output Bit 4 Audio IN/OUT Word Select Multi-channel/SPDIF Output ITU-656 VIP Data Bit 6 ITU-656 VIP Data Bit 1 Audio IN1 Serial Clock Audio IN2 Serial Clock Digital Video Transport Stream2 Data Bit 6 Digital Video Transport Stream2 Data Bit 3 System Ground Digital Video Transport Stream2 Clock Transport Stream Data Bit 6 Transport Stream Data Bit 3 Multiplexed Command or Byte Enable 3 Multiplexed Address or Data Bit 24 System Ground Multiplexed Address or Data Bit 20 Multiplexed Address or Data Bit 18
TS_DATA[7] TS_DATA[5] TS_DATA[2] TS_DATA[1] AD[27] AD[26] AD[25] VSS AD[17] AD[16] SERR AD[14] AD[10] AD[07] AD[03] AD[00] XIO_SEL[1] GPIO[4] I2S_IO_WS SPDIF_OUT DV1_DATA[6] DV1_DATA[1] I2S_IN1_SCK I2S_IN2_SCK DV2_DATA[6] DV2_DATA[3] VSS DV2_CLK TS_DATA[6] TS_DATA[3] C/BE[3] AD[24] VSS AD[20] AD[18]
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol TRDY
All pins...continued Pin AD6 Group PCI Type I/O Description Parity Error indicates data parity errors during all PCI transactions except Special Cycle. Parity Error indicates data parity errors during all PCI transactions except Special Cycle. Multiplexed Address or Data Bit 15 Multiplexed Address or Data Bit 11 Multiplexed Command or Byte Enable 0 Multiplexed Address or Data Bit 4 Multiplexed Address or Data Bit 1 External I/O Select0 General Purpose Input/Output Bit 5 Audio IN/OUT Data Bit 3 Audio IN/OUT Data Bit 0 ITU-656 VIP Data Bit 8 ITU-656 VIP Data Bit 4 ITU-656 VIP Data Bit 0 (Least Significant Bit) Audio IN1 OverSample Clock Audio IN2 OverSample Clock Digital Video Transport Stream2 Data Bit 5 Digital Video Transport Stream2 Data Bit 2 Digital Video Transport Stream2 Start of Packet Digital Video Transport Stream2 Data Valid Digital Video Transport Stream2 Error System Ground System Ground Multiplexed Address or Data Bit 23 Multiplexed Address or Data Bit 21 Multiplexed Address or Data Bit 19 Initiator Ready is asserted during writes to indicate valid data on AD[31:0]. Also asserted during reads to indicate the target is prepared to accept data. Wait states are inserted until IRDY and TRDY are both asserted. Stop is asserted to indicate a request from the target for the master to stop the current transmission. Multiplexed Command or Byte Enable 1 Multiplexed Address or Data Bit 12 Multiplexed Address or Data Bit 8 Multiplexed Address or Data Bit 5 Multiplexed Address or Data Bit 2 XIO Address Bit 25 General Purpose Input/Output Bit 7
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
PERR
AD7
PCI
I/O
AD[15] AD[11] C/BE[0] AD[04] AD[01] XIO_SEL[0] GPIO[5] I2S_IO_SD[3] I2S_IO_SD[0] DV1_DATA[8] DV1_DATA[4] DV1_DATA[0] I2S_IN1_OSCLK I2S_IN2_OSCLK DV2_DATA[5] DV2_DATA[2] DV2_SOP DV2_VALID DV2_ERR VSS VSS AD[23] AD[21] AD[19] IRDY
AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6
PCI PCI PCI PCI PCI MISC GPIO AVIF AVIF DVB DVB DVB AVIF AVIF DVB DVB DVB DVB DVB PWR PWR PCI PCI PCI PCI
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I I I I I I/O I/O I/O I/O
STOP C/BE[1] AD[12] AD[08] AD[05] AD[02] XIO_A25 GPIO[7]
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AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14
PCI PCI PCI PCI PCI PCI MISC GPIO
I/O I/O I/O I/O I/O I/O I/O I/O
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol
All pins...continued Pin AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 Group AVIF AVIF DVB DVB DVB DVB AVIF AVIF DVB DVB PWR PWR PWR PWR PCI PCI PCI PCI PCI PCI Type I/O I/O I/O I/O I/O I/O I I I I I/O I/O I/O I/O I/O I/O Description Audio IN/OUT Serial Clock Audio IN/OUT Data Bit 1 ITU-656 VIP Data Bit 9 (Most Significant Bit) ITU-656 VIP Data Bit 5 ITU-656 VIP Data Bit 2 ITU-656 VIP Data Clock Audio IN1 Data Audio IN2 Data Digital Video Transport Stream2 Data Bit 4 Digital Video Transport Stream2 Data Bit 1 System Ground System Ground System Ground System Ground Initialization Device Select provides chip select during configuration read and write transactions. Multiplexed Address or Data Bit 22 Multiplexed Command or Byte Enable 2 Frame is asserted to indicate start of bus transaction and remains asserted until final data phase begins. Device Select is asserted when a target address is decoded and remains asserted to indicate that a target device is selected. Parity supports even parity across the PCI Address/Data Bus AD[31:0]) and Command/ Byte Enable Bus (C/BE[3:0]). Bus Master drives PAR for address and write data phases. Target drives PAR for the read data phases. Multiplexed Address or Data Bit 13 Multiplexed Address or Data Bit 9 Multiplexed Address or Data Bit 6 External I/O Select2 XIO Acknowledge (EEPROM) General Purpose Input/Output Bit 6 Audio IN/OUT OverSample Clock Audio IN/OUT Data Bit 2 Multi-ch/SPDIF Input ITU-656 VIP Data Bit 7 ITU-656 VIP Data Bit 3 ITU-656 VIP Data Valid Audio IN1 Word Select Audio IN2 Word Select Digital Video Transport Stream2 Data Bit 7
I2S_IO_SCK I2S_IO_SD[1] DV1_DATA[9] DV1_DATA[5] DV1_DATA[2] DV1_CLK I2S_IN1_SD I2S_IN2_SD DV2_DATA[4] DV2_DATA[1] VSS VSS VSS VSS IDSEL AD[22] C/BE[2] FRAME DEVSEL PAR
AD[13] AD[09] AD[06] XIO_SEL[2] XIO_ACK GPIO[6] I2S_IO_OSCLK I2S_IO_SD[2] SPDIF_IN DV1_DATA[7] DV1_DATA[3] DV1_VALID I2S_IN1_WS I2S_IN2_WS DV2_DATA[7]
AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23
PCI PCI PCI MISC MISC GPIO AVIF AVIF AVIF DVB DVB DVB AVIF AVIF DVB
I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 16: Symbol
All pins...continued Pin AF24 AF25 AF26 Group DVB PWR PWR Type I Description Digital Video Transport Stream2 Data Bit 0 System Ground System Ground
DV2_DATA[0] VSS VSS
6.2.1
Multi-function pins Table 17 identifies and describes alternate signals that are available in the PNX8526. In Section 6.2 alternate signals are also identified by a hash (#) within each functional group of signals. Remark: The PNX8526 has a number of General Purpose Input Output (GPIO) pins. Some of these are dedicated pins, while others are configured as alternate signals on multi function pins, as described below. The standard function of these pins may not be required in some system configurations. For more details on GPIO functionality, see PNX8526 User Manual, Chapter 10.
Table 17: Multiplexed (MUX) pins In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function I2S_IO_OSCLK GPIO 45 AE15 AC15 AD15 AF16 AE16 AD16 R1 R2 R4 I2S_IO_SCK GPIO 46 I2S_IO_WS GPIO 47 I2S_IO_SD[3] GPIO 51 I2S_IO_SD[2] GPIO 50 I2S_IO_SD[1] GPIO 49 I2S_IO_SD[0] GPIO 48 DV_CLK2 DV_OUT2[9] SPY_OUT[9] DV_OUT2[8] SPY_OUT[8] DSU_TPC1 R3 DV_OUT2[7] SPY_OUT[7] DSU_TPC0
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Type
Description
AF15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O
Audio IN/OUT Oversample Clock General Purpose Input/Output 45 Audio IN/OUT Serial Clock General Purpose Input/Output 46 Audio IN/OUT Word Select General Purpose Input/Output 47 Audio IN/OUT Data Bit 3 General Purpose Input/Output 51 Audio IN/OUT Data Bit 2 General Purpose Input/Output 50 Audio IN/OUT Data Bit 1 General Purpose Input/Output 49 Audio IN/OUT Data Bit 0 General Purpose Input/Output 48 Digital Video Clock2 for secondary display channel from AICP Digital Video Output2, Bit 9 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 9 Digital Video Output2, Bit 8 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 8 Debug Support Unit1, TPC1 Digital Video Output2, Bit 7 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 7 Debug Support Unit0, TPC0
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Preliminary data
Rev. 01 - 6 October 2003
30 of 59
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 17: Multiplexed (MUX) pins...continued In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function DV_OUT2[6] SPY_OUT[6] DSU_PCST1[2] T2 DV_OUT2[5] SPY_OUT[5] DSU_PCST1[1] T3 DV_OUT2[4] SPY_OUT[4] DSU_PCST1[0] U1 DV_OUT2[3] SPY_OUT[3] DSU_PCST0[2] T4 DV_OUT2[2] SPY_OUT[2] DSU_PCST0[1] U2 DV_OUT2[1] SPY_OUT[1] DSU_PCST0[0] U3 DV_OUT2[0] SPY_OUT[0] DSU_CLK K2 I2S_OUT2_OSCLK DV_OUT[20] SPY_OUT[11] L3 I2S_OUT2_SCK DV_OUT[21] SPY_OUT[10] K1 I2S_OUT2_WS DV_OUT[22] DBG_EXT_STOP L4 I2S_OUT2_SD DV_OUT[23] CLK_SPY AE17 AD17 DV1_DATA[9] GPIO 42 DV1_DATA[8] GPIO 41 Type Description
T1
O O O O O O O O O O O O O O O O O O O O O O O O I/O O O I/O O I O O O I I/O I I/O
Digital Video Output2, Bit 6 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 6 Program Counter Status1, Bit 2 Digital Video Output2, Bit 5 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 5 Program Counter Status1, Bit 1 Digital Video Output2, Bit 4 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 4 Program Counter Status1, Bit 0 Digital Video Output2, Bit 3 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 3 Program Counter Status0, Bit 2 Digital Video Output2, Bit 2 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 2 Program Counter Status0, Bit 1 Digital Video Output2, Bit 1 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 1 Program Counter Status0, Bit 0 Digital Video Output2, Bit 0 for secondary display channel from AICP SPY Micro-Architecture Output signal, Bit 0 Debug Support Unit Clock Audio OUT2 Oversample Clock AICP RGB Data Bit 20 SPY Micro-Architecture Output signal, Bit 11 Audio OUT2 Serial Clock AICP RGB Data Bit 21 SPY Micro-Architecture Output signal, Bit 10 Audio OUT2 Word Select AICP RGB Data Bit 22 External Stop Request signal Audio OUT2 Data AICP RGB Data Bit 23 (Most Significant Bit) SPY Micro-Architecture Clock Output signal ITU-656 VIP Data Bit 9 (Most Significant Bit) General Purpose Input/Output 42 ITU-656 VIP Data Bit 8 General Purpose Input/Output 41
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 17: Multiplexed (MUX) pins...continued In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function DV1_DATA[7] GPIO 40 AC17 AE18 AD18 AF19 AE19 AC18 AD19 AF20 AE20 AF23 AC21 DV1_DATA[6] GPIO 39 DV1_DATA[5] GPIO 38 DV1_DATA[4] GPIO 37 DV1_DATA[3] GPIO 36 DV1_DATA[2] GPIO 35 DV1_DATA[1] GPIO 34 DV1_DATA[0] GPIO 33 DV1_VALID GPIO 44 DV1_CLK GPIO 43 DV2_DATA[7] VIP[9] DV2_DATA[6] VIP[8] TSS_DATA2 AD22 DV2_DATA[5] VIP[7] TSS_SOP2 AE23 DV2_DATA[4] VIP[6] TSS_ERR2 AC22 DV2_DATA[3] VIP[5] TSS_VALID2 AD23 DV2_DATA[2] VIP[4] TSS_CLK2 Type Description
AF18
I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I I I I I I I I I I I I I I I I
ITU-656 VIP Data Bit 7 General Purpose Input/Output 40 ITU-656 VIP Data Bit 6 General Purpose Input/Output 39 ITU-656 VIP Data Bit 5 General Purpose Input/Output 38 ITU-656 VIP Data Bit 4 General Purpose Input/Output 37 ITU-656 VIP Data Bit 3 General Purpose Input/Output 36 ITU-656 VIP Data Bit 2 General Purpose Input/Output 35 ITU-656 VIP Data Bit 1 General Purpose Input/Output 34 ITU-656 VIP Data Bit 0 (Least Significant Bit) General Purpose Input/Output 33 ITU-656 VIP Data Valid General Purpose Input/Output 44 ITU-656 VIP Data Clock General Purpose Input/Output 43 Digital Video Transport Stream2 Data Bit 7 ITU-656 VIP Data Bit 9 (Most Significant Bit) Digital Video Transport Stream2 Data Bit 6 ITU-656 VIP Data Bit 8 Digital Video Transport Stream2 Serial Data2 Digital Video Transport Stream2 Data Bit 5 ITU-656 VIP Data Bit 7 Digital Video Transport Stream2 Serial Start of Packet2 Digital Video Transport Stream2 Data Bit 4 ITU-656 VIP Data Bit 6 Digital Video Transport Stream2 Serial Error2 Digital Video Transport Stream2 Data Bit 3 ITU-656 VIP Data Bit 5 Digital Video Transport Stream2 Serial Valid2 Digital Video Transport Stream2 Data Bit 2 ITU-656 VIP Data Bit 4 Digital Video Transport Stream2 Serial Clock2
9397 750 11715
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Preliminary data
Rev. 01 - 6 October 2003
32 of 59
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 17: Multiplexed (MUX) pins...continued In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function DV2_DATA[1] VIP[3] AF24 DV2_DATA[0] VIP[2] TSS_DATA1 AD24 DV2_SOP VIP[1] TSS_SOP1 AD26 DV2_ERR VIP[0] TSS_ERR1 AD25 DV2_VALID VIP_VALID TSS_VALID1 AC24 DV2_CLK VIP_CLK TSS_CLK1 W23 Y24 DV3_DATA[7] VIP[9] DV3_DATA[6] VIP[8] TSS_DATA2 Y25 DV3_DATA[5] VIP[7] TSS_SOP2 Y26 DV3_DATA[4] VIP[6] TSS_ERR2 W24 DV3_DATA[3] VIP[5] TSS_VALID2 V23 DV3_DATA[2] VIP[4] TSS_CLK2 W25 DV3_DATA[1] VIP[3] Type Description
AE24
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
Digital Video Transport Stream2 Data Bit 1 ITU-656 VIP Data Bit 3 Digital Video Transport Stream2 Data Bit 0 ITU-656 VIP Data Bit 2 Digital Video Transport Stream2 Serial Data1 Digital Video Transport Stream2 Start of Packet ITU-656 VIP Data Bit 1 Digital Video Transport Stream2 Serial Start of Packet1 Digital Video Transport Stream2 Error ITU-656 VIP Data Bit 0 (Least Significant Bit) Digital Video Transport Stream2 Serial Error1 Digital Video Transport Stream2 Data Valid ITU-656 VIP Data Valid Digital Video Transport Stream2 Serial Valid1 Digital Video Transport Stream2 Clock ITU-656 VIP Data Clock Digital Video Transport Stream2 Serial CLock1 Digital Video Transport Stream3 Data Bit 7 ITU-656 VIP Data Bit 9 (Most Significant Bit) Digital Video Transport Stream3 Data Bit 6 ITU-656 VIP Data Bit 8 Digital Video Transport Stream3 Serial Data2 Digital Video Transport Stream3 Data Bit 5 ITU-656 VIP Data Bit 7 Digital Video Transport Stream3 Serial Start of Packet2 Digital Video Transport Stream3 Data Bit 4 ITU-656 VIP Data Bit 6 Digital Video Transport Stream3 Serial Error2 Digital Video Transport Stream3 Data Bit 3 ITU-656 VIP Data Bit 5 Digital Video Transport Stream3 Serial Valid2 Digital Video Transport Stream3 Data Bit 2 ITU-656 VIP Data Bit 4 Digital Video Transport Stream3 Serial Clock2 Digital Video Transport Stream3 Data Bit 1 ITU-656 VIP Data Bit 3
9397 750 11715
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Preliminary data
Rev. 01 - 6 October 2003
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 17: Multiplexed (MUX) pins...continued In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function DV3_DATA[0] VIP[2] TSS_DATA1 V24 DV3_SOP VIP[1] TSS_SOP1 U23 DV3_ERR VIP[0] TSS_ERR1 V25 DV3_VALID VIP_VALID TSS_VALID1 V26 DV3_CLK VIP_CLK TSS_CLK1 AB23 AC25 AB24 AA23 AC26 AB25 AB26 Y23 TS_DATA[7] GPIO 29 TS_DATA[6] GPIO 28 TS_DATA[5] GPIO 27 TS_DATA[4] GPIO 26 TS_DATA[3] GPIO 25 TS_DATA[2] GPIO 24 TS_DATA[1] GPIO 23 TS_DATA[0] GPIO 22 TS_SD AA24 AA25 AA26 TS_SOP GPIO 31 TS_VALID GPIO 32 TS_CLK GPIO 30
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Type
Description
W26
I I I I I I I I I I I I I I I O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O I/O O I/O O I/O
Digital Video Transport Stream3 Data Bit 0 ITU-656 VIP Data Bit 2 Digital Video Transport Stream3 Serial Data1 Digital Video Transport Stream3 Start of Packet ITU-656 VIP Data Bit 1 Digital Video Transport Stream3 Serial Start of Packet1 Digital Video Transport Stream3 Error ITU-656 VIP Data Bit 0 (Least Significant Bit) Digital Video Transport Stream3 Serial Error1 Digital Video Transport Stream3 Data Valid ITU-656 VIP Data Valid Digital Video Transport Stream3 Serial Valid1 Digital Video Transport Stream3 Clock ITU-656 VIP Data Clock Digital Video Transport Stream3 Serial Clock1 Transport Stream Data Bit 7 General Purpose Input/Output 29 Transport Stream Data Bit 6 General Purpose Input/Output 28 Transport Stream Data Bit 5 General Purpose Input/Output 27 Transport Stream Data Bit 4 General Purpose Input/Output 26 Transport Stream Data Bit 3 General Purpose Input/Output 25 Transport Stream Data Bit 2 General Purpose Input/Output 24 Transport Stream Data Bit 1 General Purpose Input/Output 23 Transport Stream Data Bit 0 General Purpose Input/Output 22 Transport Stream Serial Data Out Transport Stream Start of Packet (Parallel/Serial) General Purpose Input/Output 31 Transport Stream Data Valid (Parallel/Serial) General Purpose Input/Output 32 Transport Stream Clock (Parallel/Serial) General Purpose Input/Output 30
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Preliminary data
Rev. 01 - 6 October 2003
34 of 59
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 17: Multiplexed (MUX) pins...continued In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function PCI_REQ_A*[1] GPIO 57 AA3 PCI_REQ_B* GPIO 58 Y4 PCI_GNT_A* GPIO 59 AA4 PCI_GNT_B* GPIO 60 AF12 AC13 AD13 AF13 AE13 U24 U25 T23 U26 XIO_SEL[2]* GPIO 54 XIO_SEL[1]* GPIO 53 XIO_SEL[0]* GPIO 52 XIO_ACK* GPIO 55 XIO_A25* GPIO 56 UA1_TX GPIO 12 UA1_RX GPIO 13 UA2_TX GPIO 14 UA2_RX ICAM1_SETVPP GPIO 15 T24 UA2_RTSN ICAM1_C8 GPIO 16 T25 UA2_CTSN ICAM1_C4 GPIO 17 Type Description
AA2
I/O I/O I/O I/O I/O I/O I/O I/O O I/O O I/O O I/O I I/O O I/O O I/O I I/O O I/O I O I/O O I I/O I I/O I/O
Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where internal arbiter is configured. General Purpose Input/Output 57 Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where internal arbiter is configured. General Purpose Input/Output 58 Auxiliary Arbitration Grant_A is asserted to indicate bus access has been granted to an external PCI master. Used where internal arbiter is configured. General Purpose Input/Output 59 Auxiliary Arbitration Grant_B is asserted to indicate bus access has been granted to an external PCI master. Used where internal arbiter is configured. General Purpose Input/Output 60 External MMIO Select 2 General Purpose Input/Output 54 External MMIO Select 1 General Purpose Input/Output 53 External MMIO Select 0 General Purpose Input/Output 52 XIO Acknowledge (EEPROM) General Purpose Input/Output 55 XIO Address bit 25 General Purpose Input/Output 56 UART1 Transmit General Purpose Input/Output 12 UART1 Receive General Purpose Input/Output 13 UART2 Transmit General Purpose Input/Output 14 UART2 Receive ICAM1 VPP**[2] General Purpose Input/Output 15 UART2 Request To Send ICAM1 C8** General Purpose Input/Output 16 UART2 Clear To Send ICAM1 C4 General Purpose Input/Output 17
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Preliminary data
Rev. 01 - 6 October 2003
35 of 59
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 17: Multiplexed (MUX) pins...continued In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function SSI_SCLK_CTSN UART CTS GPIO 21 V2 SSI_FS_RTSN UART RTS GPIO 20 U4 V3 N26 N24 N23 M26 AE14 AF14 AD14 AC14 C5 B4 D5 C4 P25 P24 P26 N25 P23 SSI_RXD GPIO 19 SSI_TXD GPIO 18 ICAM2_C4 GPIO 11 ICAM2_C8 GPIO 10 ICAM2_SETVPP GPIO 9 GPIO 8 GPIO 7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 Boot Mode [2] GPIO 2 Boot Mode [1] GPIO 1 Boot Mode [0] GPIO 0 SC2_OFFN ICAM2_DETECT SC2_CMD ICAM2_SETVCC SC2_RST ICAM2_RESET SC2_SCCK ICAM2_CLK SC2_DA ICAM2_C7
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Type
Description
V1
I I I/O I O I/O I I/O O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I O O O O O O I/O I/O
Synchronous Serial Interface CLock Input UART2 Clear To Send General Purpose Input/Output 21 Synchronous Serial Interface Frame Sync UART2 Request To Send General Purpose Input/Output 20 Synchronous Serial Interface Receive General Purpose Input/Output 19 Synchronous Serial Interface Transmit General Purpose Input/Output 18 ICAM2 C4 General Purpose Input/Output 11 ICAM2 C8 General Purpose Input/Output 10 ICAM2 VPP General Purpose Input/Output 9 General Purpose Input/Output 8 General Purpose Input/Output 7 General Purpose Input/Output 6 General Purpose Input/Output 5 General Purpose Input/Output 4 General Purpose Input/Output 3 Select Configuration Bit 2 during System Reset General Purpose Input/Output 2 Select Configuration Bit 1 during System Reset General Purpose Input/Output 1 Select Configuration Bit 0 during System Reset General Purpose Input/Output 0 Smartcard Off ICAM2 Detect Smartcard Command ICAM2 VCC Smartcard Reset ICAM2 Reset Smartcard Clock ICAM2 Clock SmartCard2 Data ICAM2 C7
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PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 17: Multiplexed (MUX) pins...continued In this table,"Type" reflects mux pin function only. A pin may have other "Type" capabilities as noted in its functional group. See Section 6.2 for more details. Pin MUX contacts Primary signal and Alternate Function SC1_OFFN ICAM1_DETECT R23 R24 R26 T26 SC1_CMD ICAM1_SETVCC SC1_RST ICAM1_RESET SC1_SCCK ICAM1_CLK SC1_DA ICAM1_C7
[1] [2]
Type
Description
R25
I I O O O O O O I/O I/O
Smartcard Off ICAM1 Detect Smartcard Command ICAM1 VCC Smartcard Reset ICAM1 Reset Smartcard Clock ICAM1 Clock Smartcard1 Data ICAM1 C7
*These pins are included in the XIO set. Refer to PNX8526 User Manual, Chapter 8 for additional functions. **The ICAM1_SETVPP and ICAM1_C8 signals are automatically selected when the ICAM function is selected. Refer to Table 18 (Offset 0x04 D600 IO_MUX_CTR). Selecting GPIO mode will disable this ICAM functionality.
7. Functional description
Figure 3 shows a block diagram of a typical PNX8526-based system. The system shown is a "standalone system" which uses the internal MIPS host. The PNX8526 runs on a single 27 MHz xtal from which all internal and external clocks are derived by on-chip synthesizers. The PNX8526 boots directly from attached Flash memory or ROM. If desired, custom boot methods can be programmed using the optional I2C boot EEPROM. The PNX8526 has three Digital Video inputs that accept digitized analog video (ITU-656), although only two ITU-656 streams can be processed simultaneously. Two of these inputs, DV2 and DV3, can also accept scrambled transport streams. The DV inputs support parallel transport stream formats. In addition, a single incoming 1394 transport stream is supported. Two selected transport streams can undergo internal de-scrambling and decoding. Based on the system implementation, one or both transport streams may pass through Point of Deployment (POD) or Common Interface (CI) conditional access modules before transfer into the PNX8526. Either a single companion IC, such as the SCM Microsystems CIMaXTM, or two CIMaXTM chips can be used. In the latter case, it is possible to handle dual decoding no matter which conditional access system is used. The PNX8526 contains on-chip DVB, MULTI2 and DES hardware de-scramblers, as well as an ICAM verifier. The entitlement system for these de-scramblers is provided via two Smartcard interfaces. The TM32 CPU does further processing on the result of the transport stream de-mux.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
For MPEG2 video, a slice level HL MPEG2 video decoder performs the majority of the MPEG2 algorithm. This MPEG decoder is capable of full-resolution decoding. The TM32 CPU does all MPEG2 processing above the slice level. Two simultaneous SD streams or one HD stream may be processed. All audio processing is done by the TM32 CPU. Compressed audio will be present in memory from either the transport stream de-multiplex or from the SPDIF input port. The SPDIF input port is intended primarily for DTV applications where a SPDIF source is available from an external source device, such as a DVD player. PCM (stereo sample) audio is present in memory from the I2S input ports or SPDIF input. Two AC-3 (or equivalent) compressed audio streams may be decoded simultaneously. The TM32 CPU may also process effects, enhancements and mix the audio data. Multi-channel compressed audio or down-mixed stereo PCM audio is transmitted over the SPDIF output interface. Multi-channel audio samples are Dolby Pro LogicTM down-mixed into the two stereo I2S interfaces to the PNX8510 companion IC. In addition to the two I2S inputs and two I2S outputs, a bi-directional I2S interface is provided. This allows connection of other audio inputs or outputs-headphones, for example. Note that there is not enough compute power to support encoding of multi-channel compressed audio simultaneous with video processing. So the multi-channel compressed audio transmitted over SPDIF must be from one of the original compressed sources. Graphics rendering may be accomplished with the MIPS or the TM32 CPU by utilizing the 2D Drawing and DMA engine. This engine can perform fast area fills, 3-operand bitblt, monochrome data expansion, and lines. It can also be used as a generic DMA engine to transfer data between memory locations on a byte-aligned basis. An alpha bitblt capability is also provided to allow for anti-aliased text and lines as well as source/destination blending operations. Once all video and graphics data for specific fields or frames has been generated in memory, the video display pipeline starts processing those images for display. The video processing functions include 6-tap horizontal/vertical scaling, anti-flicker filtering, and de-interlacing (when progressive output is required). The processed images are then combined for each output. Up to four surfaces of any supported format may be combined to produce the primary display output. Up to two surfaces are combined to produce the secondary output. Compositing of more surfaces for future video algorithms is possible by using the TM32 CPU and/or the memory based scaler prior to invoking the compositing/display engine. This is subject to CPU and memory bandwidth availability. The PNX8526 contains a 1394 interface with 5C copy protection. The PNX8526 1394 can simultaneously transmit two transport streams while receiving one transport stream. The transmitted streams can be partial transport streams (created by PID filtering of an input) or one of the two streams can be software generated. In the case of receiving a scrambled 1394 transport stream input, the stream can either use the on-chip de-scramblers, or may be routed to the external companion CA IC for de-scrambling by the POD/CI CA module(s). The PNX8526 contains a variety of peripheral interfaces to support both ASTB and DTV requirements. There are two Smartcard interfaces, two USB ports, two I2C ports, one IrDA Data UART and two general purpose UARTs, one of which (UART3) is multiplexed with an SSI interface for soft modem support. The PNX8526 also contains an integrated IDE controller, which only requires an external isolation buffer
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PNX8526
Programmable Source Decoder with Integrated Peripherals
to implement a full disk interface with sustained speeds up to 10 MB/s. A third-party PCI Super I/O chip may be utilized to provide peripheral functionality not contained on the PNX8526. Functions such as IEEE-1284, 10/100 Ethernet, floppy drive support, UDMA66 IDE controllers and others are currently available in low-cost, commercially available parts.
handbook, full pagewidth VCR to Dig
to HDTV set from ext. tuner
IEEE 1394
PHY
16/32/64 MB SDRAM 64-bit
transport stream
1394 TS (output)
DV_OUT1 DV_OUT2
10 10
3 1 1
RGB or Y/C CVBS Y C (CVBS) A1 R/L A2 R/L GPIO
OOB in POD-1/ NRSS-B/CI OOB out POD-2/ NRSS-B/CI CA INTERFACE IC I2S_OUT1 DV3 (656/TS in) I2S_OUT2 I2C-2 27 MHz transport stream SSI/UART3 analog video 711X DV2 (656/TS in) SPDIFOUT DV1 (656 in) I2S_IN1/2 SPDIFIN GPIO OPTIONAL BOOT EEPROM XIO_SEL0 I2S I/O GPIO I2C-1 1 I2S > = 12 s/w I/O pins I2C bus I2C
PNX8510
1 2 2 5
PNX8526
ANALOG FRONT-END OR MODEM SPDIF out aux. audio PSTN
transport stream analog video stereo audio (2x) SPDIF in IR remote USB (2x) UART2 IrDA data (UART1) smartcard (2x) 711X
TDA8004
SC1 & SC2
PCI-XIO8 expansion bus
DOCSIS MODEM
PCI SUPER I/O IDE UDMA66 LAN 1284
BUFFER IDE 10 MB/s
FLASH
MCE541
Fig 3. PNX8526-based system block diagram
8. I/O multiplexer control register
The I/O Multiplexer Control register is used to configure the multi function pins to alternate functions as described in Table 17. Control is achieved via the Global 2 register IO_MUX_CTRL Table 18.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 18: Bit 31:15 14
Global 2 registers Access Value Description Ignore during writes and read as zeroes. R/W 0x0 I2S_IO Audio mode: 0 = Select I2S_IO as Audio Out. 1 = Select I2S_IO as Audio In.
Symbol Not used AIO_MUX_SEL
0x04 D600 IO_MUX_CTRL
13
SSI_SEL
R/W
0x0
SSI or UART3 mode: 0 = Select UART3. 1 = Select SSI.
12
RGB24_SEL
R/W
0x0
Audio Out2 or RGB mode: 0 = Select Audio Out2. 1 = Select RGB (DV_OUT [23:20]).
11:10
SMCRD2_MUX_CTRL
R/W
0x0
ICAM or SmartCard2 mode: 00 = SmartCard1 module ports go to SmartCard2 pins. 01 = SmartCard2 module ports go to SmartCard2 pins. 10 = ICAM1 module ports go to SmartCard2 pins. 11 = ICAM2 module ports go to SmartCard2 pins.
9:8
SMCRD1_MUX_CTRL
R/W
0x0
ICAM or SmartCard2 mode: 00 = SmartCard1 module ports go to SmartCard1 pins. 01 = SmartCard2 module ports go to SmartCard1 pins. 10 = ICAM1 module ports go to SmartCard1 pins. 11 = ICAM2 module ports go to SmartCard1 pins.
7 6:4
Not used VIP2_MUX_CTRL[2:0] R/W
0x0
Ignore during writes and read as zeroes. VIP2 module selection: 000 = VIP data from DV1 port 001 = VIP data from DV2 port 010 = VIP data from DV3 port 011 = VIP data from DV_OUT1(AICP1) port 100 = 1394 data from link core
3 2:0
Not used VIP1_MUX_CTRL[2:0] R/W
0x0
Ignore during writes and read as zeroes. VIP1 module selection: 000 = VIP data from DV1 port 001 = VIP data from DV2 port 010 = VIP data from DV3 port 011 = VIP data from DV_OUT2 (AICP2) port 100 = 1394 data from link core
9. Power supply sequencing
Power application and power removal should obey the following rules:
9.1 Power on sequence * Apply power to VDD 1.26 V * Allow VDD 1.26 V to stabilize (approx.100 ms recommended) * Apply power to VDD 3.3 V
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PNX8526
Programmable Source Decoder with Integrated Peripherals
9.2 Power off sequence * Power may be removed from VDD 3.3 V and VDD 1.26 V at the same time * Otherwise remove VDD 3.3 V followed by 1.26 V
10. Limiting values
Table 19: Tamb Tstg Tj Maximum ratings Min 0 -40 -0.5 -0.5 1.46 0.93 1.66 3.0 1.20 Max 70 +125 100 5.5 1.76 1.06 1.79 10 3.6 1.32 2 1 1.5 Typical Unit C C C V V V V V V V V W W kV Ambient temperature Storage temperature Junction temperature 3-volt I/O pin voltage with respect to VSS 5-volt tolerant I/O pin voltage with respect to VSS I/O with Non-Schmitt trigger input voltage threshold I/O with Schmitt trigger input threshold VILT I/O with Schmitt trigger input threshold VIHT I/O transient pin voltage DC supply voltage (VDD I/O pad) DC supply voltage (VDDC core logic) Dynamic Power Dissipation Static Power Dissipation (AICP off) Electrostatic Discharge (Human Body Model) Symbol Parameter
VDD+0.5 -
11. Thermal characteristics
PNX8526 can be used in different environments creating different junction temperatures. The thermal resistance from junction to ambient (i.e. ja) of the PNX8526 in its HBGA456 package is around 11.7 C/W. This value is acheived using natural convection, no external heatsink and using a JEDEC defined high-conductive board (see JEDEC standards 51-2 and 51-7 for details). Given the power dissipation of the PNX8526 and the ambient temperature inside the enclosure, the expected junction temperature can be calculated using the following equation: Tj = Tamb + P x Rth(j-a) In some applications the junction temperature may be judged too high, reducing the acceptable lifetime (see Section 15). However cooling can be improved by fitting an additional external heatsink, or increasing the airflow around the device. Table 20 shows the improvements that can be expected if these measures are taken.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 20: PNX8526 thermal data Heatsink size = 37 x 37 x 10 mm PNX8526 Thermal resistance Rth(j-a) (C/W) Airflow 0 m/s Standard With external h'sink 11.7 9.5 1 m/s 10.0 7.6 2 m/s 8.5 6.3
12. Static characteristics
The characteristics listed in the following tables apply to standard operating conditions, unless otherwise noted. All voltages are referenced to VSS (0V Ground). Positive current flows into the referenced pin. The standard operating voltage range is VDD = 3.3 0.3 VDC and VDDC = 1.26 0.06 VDC. All digital I/O pins are 3.3 V tolerant. In all cases described below, digital VDD = 3.3 V+ 5% and operating temperature is 0 to 70 C. All AC timings are based on a 30 pF test load and are measured at a 1.6 V threshold (see Figure 4) Actual I/O voltage threshold is dependant on pad type e.g., Schmitt trigger input (see Section 6.1).
handbook, 4 columns
2.4 V 1.6 V 0.8 V
MCE542
Fig 4. General AC characteristics
The AC voltage characteristics for active signal pins of the controller are listed in Table 21. Signal names for the PCI bus configuration are listed, as well as the minimum and maximum voltage, current, and capacitance for each pin.
Table 21: Symbol
VIL
Digital AC/DC characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Current Output High Current Min -0.5 2.4 Vss 2.4 Max +0.8 Vdd + 0.5 Vss + 0.4 5 -5 8 -8 12 -12 14 -14 Typical Unit V V V V mA mA mA mA mA mA mA mA
VIH VOL VOH IOL1
[1]
IOH1 IOL2[2] IOH2 IOL3
[3]
IOH3 IOL4[4] IOH4
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PNX8526
Programmable Source Decoder with Integrated Peripherals
Digital AC/DC characteristics...continued Parameter Output Tri-state Current Input Capacitance Power Supply Current Power Supply Current
lOL1 (4mA): I2S_IN1_SCK, I2S_IN1_WS, I2S_IN2_SCK, I2S_IN2_WS, I2S_OUT1_SCK, I2S_OUT1_WS, I2S_OUT1_SD, I2S_OUT2_SD, DV1_DATA[9:0], DV1_VALID, DV1_CLK, DBG_TDO, JTAG_TDO, XTAL_OUT, UA1_TX, UA1_RX, UA2_TX, UA2_RX, UA2_RTS, UA2_CTS, SC1_DA, SC1_CMD, SC1_RST, SC1_SCCK, SC2_DA, SC2_CMD, SC2_RST, SC2_SCCK, SSI_SCLK_CTSN, SSI_FS_RTSN, SSI_RX, SSI_TX, USB_DM[1:0], USB_DP[1:0], USB_BUS_PWR
Table 21: Symbol IOZ
Min -
Max 0.041 3.5 1.5 0.2
Typical 0.9 0.13
Unit mA pF A A
CIN, COUT, CI/O ICC ICP
[1]
[2]
IOL2 (8mA): DV_OUT1[9:0], DV_OUT2[9:0], DV_CLK1, DV_CLK2, HSYNC, VSYNC, BLANK, I2S_IN1_OSCLK, I2S_IN2_OSCLK, I2S_IO_OSCLK, I2S_IO_SCK, I2S_IO_WS, I2S_IO_SD[3:0], I2S_OUT1_OSCLK, I2S_OUT2_OSCLK, I2S_OUT2_SCK, I2S_OUT2_WS, TS_DATA[7:0], TS_SOP, TS_VALID, TS_CLK, PHY_DATA[7:0], PHY_CTL[1:0], PHY_LREQ, MM_DATA[63:0], MM_DQMM_[7:0], MM_CKE, I2C1_SCL, I2C1_SDA, I2C2_SCL, I2C2_SDA, GPIO[11:0], SYS_RSTN_OUT, XIO_SEL[2:0], XIO_ACK, XIO_AD25
[3]
IOL3 (12mA): PCI_AD[31:0], PCI_CBE[3:0], PCI_DEVSEL, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_STOP, PCI_PERR, PCI_PAR, PCI_INTA, PCI_REQ, PCI_GNT, PCI_REQ_A, PCI_REQ_B, PCI_GNT_A, PCI_GNT_B, PCI_SERR,MM_WE, PLL_OUT,
[4]
IOL4 (14mA): SPDIF_OUT, MM_CLK[1:0], MM_ADDR[11:0], MM_BA[1:0], MM_CS, MM_RAS, MM_CAS
The pin names used in the above notes are the primary names for PCI configurations. Output signals multiplexed on some pins have the same drive level. VDD = 3.3 V +5%, Operating Temperature 0 C to 70 C
13. Dynamic characteristics
13.1 Reset timing
tLOW
handbook, 4 columns
RESET_IN
MCE543
Fig 5. Reset timing Table 22: Symbol tLOW Reset timing Parameter RESET_IN active pulse width (after stable power) Min 400 Units
s
13.2 Peripheral Controller Interface (PCI) timing
For additional timing diagram information on XIO and IDE interfaces, see PNX8526 User Manual, Chapter 8.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
handbook, 4 columns
PCI CLOCK tsu PCI-XIO INPUTS tOD(max) tOD(min) th
PCI-XIO OUTPUTS
MCE544
Fig 6. PCI timing Table 23: Symbol tsu th th tsu th Table 24: Symbol tOD tOD tOD tOD tOD
[1]
PCI CLK-referenced input timing Parameter PCI_AD[31:0], CBE[3:0], PCI_FRAME, PCI_IRDY PCI_AD[31:0] hold PCI_C/BE[3:0], PCI_FRAME, PCI_IRDY, PCI_IDSEL hold PCI_GNT setup PCI_GNT hold PCI CLK-referenced output valid timing Parameter PCI_AD[31:0], PCI_CBE[3:0] PCI_DEVSEL, PCI_PAR PCI_STOP PCI_TRDY PCI_REQ Min 2 2 2 2 2 Max 11 11 11 11 12 Unit ns ns ns ns ns Min 7 0 0 10 0 Unit ns ns ns ns ns
Minimum delay is the minimum time after the clock edge that a valid signal state from the previous cycle will begin transition to the next state (become invalid). Maximum delay is the maximum time after the clock edge that a signal state is valid for the next cycle.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
13.3 Main Memory Interface (MMI) timing
MCLK(f)
handbook, 4 columns
tclk(L)
tclk(H)
MMI CLK tcs MMI CONTROL & tch
MMI DATA
valid
tdsi, tdso tdhi, tdho
MCE545
Fig 7. MMI Timing Table 25: tcs tch tdso tdho tdsi tdhi tclk(L) tclk(H) MMI timing (MCLK-referenced) Min Max Unit 1.5 0.8 1.5 0.8 0 2.0 2.9 2.9 166 ns ns ns ns ns ns ns ns MHz Setup time with reference to clock Hold time with reference to clock MMI data output setup time with reference to clock (write cycle) MMI data output hold time with reference to clock (write cycle) MMI data input setup with reference to clock (read cycle) MMI data input hold with reference to clock (read cycle) Clock low time Clock high time
Symbol Parameter
MCLK(f) MMI_CLK[1:0]
13.4 General Purpose Input/Output (GPIO) timing
handbook, 4 columns
GPIO
1.5 V
MIN
MCE546
Fig 8. GPIO timing Table 26: Parameter GPIO as input GPIO as output
[1]
GPIO timing Min 10 75 Max Unit ns[1] ns
If GPIO is intended to be timestamped, the minimum pulse width is 75 ns
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Programmable Source Decoder with Integrated Peripherals
13.5 Universal Asynchronous Receiver/Transmitter (UART) timing
handbook, 4 columns
UART TX/RX RTSN/CTSN
1.5 V
MIN
MCE547
Fig 9. UART timing Table 27: Parameter UART TX UART RX UART RTSN UART CTSN
[1] Max baud rate: 230 kBs
UART CLK-referenced output timing Min 4.3 4.3 4.3 4.3 Max Unit s[1] s s s
13.6 Synchronous Serial Interface (SSI) timing
tclk(L)
handbook, 4 columns
tclk(H)
SSI_SCLK tcs tch
CONTROL
DATA
valid
tdsi, tdso tdhi, tdho
MCE548
Fig 10. SSI timing Table 28: Symbol tcs tch tdso tdho tdsi tdhi tclk(L) tclk(H) SSI interface timing (MCLK-referenced) Parameter Setup time with reference to clock Hold time with reference to clock Data output setup time with reference to clock Data output hold time with reference to clock Data input setup with reference to clock Data input hold with reference to clock Clock low time Clock high time Min 3 2 3 2 1.0 1.0 25 25 Max Unit ns ns ns ns ns ns ns ns
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Programmable Source Decoder with Integrated Peripherals
13.7 I2C-bus timing
tHIGH
handbook, 4 columns
tLOW
SCL tsu(STA) th(STA)
SDA
SCL th(SDA) tdv(STO) tdv(SDA) tsu(SDA) SDA valid
MCE549
Fig 11. I2C-bus timing Table 29: Symbol SCL tsu(STA) th(STA) tLOW tHIGH tsu(SDA) th(SDA) tdv(SDA) tdv(SDO) I2C-bus timing Parameter SCL clock frequency Start condition setup time Start condition hold time SCL LOW time SCL HIGH time Data setup time Data hold time SCL LOW to data out valid SCL HIGH to data out Min 1 1 1 1 100 0 1 Max 400 0.5 Unit kHz s s s s ns ns s s
13.8 IEEE 1394 Phy-Link interface
f1394
handbook, full pagewidth
CLK_1394 tsu 1394 Link Input Port tp 1394 Link Output Port
MCE550
th
Fig 12. IEEE 1394 Phy-Link interface timing
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Programmable Source Decoder with Integrated Peripherals
IEEE 1394 Phy-Link interface signals Parameter CLK_1394 frequency Input setup time for PHY_DATA[7:0], PHY_CTL[1:0] Input hold time Output propagation delay for PHY_DATA[9:0], PHY_LREQ, PHY_CTL[1:0] Min 6 0 Max 9 Unit ns ns ns 49.147 49.157 MHz
Table 30: Symbol f1394 tsu th tp
13.9 I2S audio input & output timing
fAl_SCK
handbook, 4 columns
Al_SCK tsu(CLK) th(CLK) Al_SD Al_WS
valid
tws(SCK) Al_WS valid
MCE551
Fig 13. I2S audio input timing Table 31: Symbol fAI_SCK tsu(CLK) th(CLK) tws(SCK)
[1]
I2S audio input Parameter Audio In AI_SCK clock frequency Input Setup Time to AI_SCK (Audio interface as slave) Input Hold Time from AI_SCK (Audio interface as slave) AI_SCK to AI_WS Min Max Unit 3 2 2 20 10 MHz ns ns ns
Timing measurements are done with respect to the SCK clock edge. The PNX8526 is the source of AI_WS.
handbook, 4 columns
AO_SCK tSCK(DV)
AO_SD
valid
tws(SCK) AO_WS valid
MCE552
Fig 14. I2S audio output timing
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Programmable Source Decoder with Integrated Peripherals
I2S audio output Parameter Audio Out to AO_SCK clock frequency AO_SCK to AO_SC valid Input Setup Time to AO_SCK (Audio interface as slave) Input Hold Time from AO_SCK (Audio interface as slave) AO_SCK to AO_WS Min Max Unit 2 2 2 20 10 MHz ns ns ns ns
Table 32: Symbol AO_SCK tSCK(DV) tsu(SCK) th_SCK tws(SCK)
13.10 Sony Philips Digital Interface (SPDIF) timing
handbook, 4 columns
tHIGH
tLOW
MCE553
Fig 15. SPDIF timing Table 33: Symbol tHIGH tLOW SPDIF timing Parameter CLK High Time (PCI) CLK Low Time (PCI) Min Typical 5.2 5.2 Max Unit s s
13.11 Digital Video Output (DV Out) timing
handbook, 4 columns
DV_CLK tsu(CLK) HSYNC VSYNC BLANK th(CLK)
valid
tCLK(DV) DV_OUT (Data) valid
MCE554
Fig 16. DV Out timing Table 34: Symbol DV_CLK tCLK(DV) tsu(CLK) th(CLK) DV Out timing Parameter Video out clock frequency DV_CLK to DV_OUT VSYNC Setup Time to DV_CLK (as input) CRT Control Hold Time from DV_CLK HSYNC, VSYNC, BLANK Min 27 -3.7 3 0 Max 0 Unit MHz[1] ns ns ns
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Programmable Source Decoder with Integrated Peripherals
DV_CLK period is programmable via the internal PLL
[1]
13.12 Digital Video Input (DV Input) timing
fDVB
handbook, 4 columns
CLOCK tsu INPUTS (DATA, SOP, ERROR, VALID) 1.5 V
1.5 V th 1.5 V
MCE555
Fig 17. DV Input timing Table 35: Symbol tsu th fDVB DV Input timing (VDICLK-referenced) Parameter [7:0] setup [7:0] hold Clock Min 3 3 Typical 27 Max Unit ns ns MHz
13.13 Transport Stream Output (TSO) timing
handbook, 4 columns
CLOCK
tsu OUTPUT (DATA, SOP, VALID)
th
MCE556
Fig 18. TSO timing Table 36: Symbol tsu th TSO timing Parameter Data setup Data hold Min 3 0 Typical Max Unit ns ns
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PNX8526
Programmable Source Decoder with Integrated Peripherals
13.14 JTAG test contacts
handbook, 4 columns
tsu(TCK) TDI TMS
th(TCK)
valid
TCK tclk(TDO)
TDO
valid
MCE557
Fig 19. JTAG timing Table 37: Symbol tclk(TDO) tsu(TCK) th(TCK) JTAG timing Parameter JTAG_TCK to JTAG_TDO Valid delay Input Setup Time JTAG_TCK Input Setup Time JTAG_TCK Min TBD TBD TBD Max Unit
14. Delta compared to PNX8525
There are a number of differences between the PNX8526 and the PNX8525 with respect to the physical interfacing of the device. These differences are described in Table 38.
Table 38: Differences - 8525 / 8526 PNX8525 1.8 V 5% I2C-bus pads GPIO pads with schmitt trigger and pull-ups IEEE-1394 pads GPIO pads with schmitt trigger and pull-ups PCI Interface Supports 5 V tolerant interface with 3.3 V signalling System reset output (SYS_RSTN_OUT) Drive capability 12 mA Clock output (PLL_OUT) Drive capability 12 mA SPDIF output
9397 750 11715 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Characteristic Core supply voltage
PNX8526 1.26 V 0.06 V Special I2C pads designed to meet the I2C specification Special IEEE-1394 pads designed to meet the IEEE-1394 Link to Phy specification No 5 V tolerant interface, all signals limited to 3.3 V
Drive capability 8 mA Drive capability 8 mA
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PNX8526
Programmable Source Decoder with Integrated Peripherals
Table 38:
Differences - 8525 / 8526...continued PNX8525 Drive capability 16 mA PNX8526 Drive capability 14 mA Drive capability 5 mA, INputs support Hysteresis Drive capability 5 mA Hysteresis on inputs supported No 5 V tolerant signalling. Drive capability 14 mA
Characteristic
DV1 port, SSI, Uart2, Smart Card1, Smart Card2 Drive capability 4 mA I2S CLK and WS Drive capability 4 mA TS interface and I2S data lines Hysteresis on inputs not supported SDRAM interface Supports 5 V tolerant signalling, with 3.3 V drive. (AD[11:0],CLK[1:0], RAS,CAS, CS, BA[1:0] have drive capability 16 mA) XIO SEL[2:0], ACK, A25 Drive capability 12 mA Peripheral power supply Single connection on PCB for all VDD bondpads Requires separation of VDDC into 3 segments, each segment filtered and star connected back to source.[1] Core power supply Single connection on PCB for all VDDC bondpads Requires separation of VDDC into 2 segments, each segment filtered and star connected back to source.[2] Drive capability 8 mA
[1]
The new connections are VDD1 - The I/O supply connection VDD2 - Analogue clock generation unit (CAB-Custom Analogue Block) VDD3 - TrimediaTM clock generation PLL
[2]
The new connections are VDDC1 - Main core supply connection VDDC2 - 1.728GHz PLL supply connection
15. Lifetime versus temperature
The relationship between operating (junction) temperature and the expected lifetime of a device is shown in Figure 20.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
handbook, halfpage
25
MGX461
useful life (years)
20
15
10
5
0 100
105
110
115
120 125 Tj (C)
Useful life (yrs) vs junction temperature (C). 1% cumm. fails, 8 hrs/day.
Fig 20. Lifetime dependency to temperature
Referring to Figure 20, at a junction temperature of 110 C a 10 year lifetime can be expected (8 hours/day). If increased to 125 C, lifetime can be reduced to 4 years. Junction temperature can be influenced by following the guidelines in Section 11.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
16. Package outline
HBGA456: plastic thermal enhanced ball grid array package; 456 balls; body 35 x 35 x 1.8 mm; heatsink
SOT610-1
D D1
B A
ball A1 index area A j E1 E A2 A1
detail X
e1 e
AF AD AB Y V T P M K H F D B AE AC AA W U R N L J G E C A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 1/2 e 1/2 e
C b
v M C A B w M C
y1 C
y
e
e2
shape optional (4x)
X 10 scale 20 mm
0 DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.6 A1 0.7 0.5 A2 1.90 1.65 b 0.9 0.6 D 35.2 34.8 D1 30.75 29.75 E 35.2 34.8 E1 30.75 29.75 e 1.27
e1
e2
j 26 22
v 0.3
w 0.15
y 0.2
y1 0.35
31.75 31.75
OUTLINE VERSION SOT610-1
REFERENCES IEC 144E JEDEC MS-034 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 00-12-13 02-01-30
Fig 21. HBGA package outline
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Preliminary data
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
17. Soldering
17.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended.
17.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 220 C (SnPb process) or below 245 C (Pb-free process)
-- for all BGA and SSOP-T packages -- for packages with a thickness S 2.5 mm -- for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
17.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
* For packages with leads on two sides and a pitch (e):
-- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; -- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
17.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
17.5 Package related soldering information
Table 39: Package[1] BGA, LBGA, LFBGA, SQFP, SSOP-T[3], TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP PMFP[8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[4] Reflow[2] suitable suitable
suitable not recommended[5][6] not recommended[7] not suitable
suitable suitable suitable not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
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Preliminary data
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PNX8526
Programmable Source Decoder with Integrated Peripherals
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Hot bar or manual soldering is suitable for PMFP packages.
[3]
[4]
[5] [6] [7] [8]
18. Revision history
Table 40: Rev Date 01 20031006 Revision history CPCN Description Preliminary data (9397 750 11715)
9397 750 11715
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Preliminary data
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PNX8526
Programmable Source Decoder with Integrated Peripherals
19. Data sheet status
Level I II Data sheet status[1] Objective data Product status[2][3] Development Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes - Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Preliminary data Qualification
III
Product data
Production
[1] [2]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status
[3]
20. Definitions
Short-form specification - The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition - Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information - Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
22. Licenses
Purchase of Philips I2C components Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
21. Disclaimers
Life support - These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
23. Trademarks
Nexperia - is a trademark of Koninklijke Philips Electronics N.V. TriMedia - is a trademark of TriMedia Technologies Inc. OpenCable - is a trademark of Cable Television Laboratories Inc. Dolby ProLogic - is a registered trademark of Dolby Laboratories CIMaX - is a registered trademark of SCM Microsystems Inc.
24. Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com.
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PNX8526
Programmable Source Decoder with Integrated Peripherals
Contents
1 2 3 4 5 6 6.1 6.2 6.2.1 7 8 9 9.1 9.2 10 11 12 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Multi-function pins. . . . . . . . . . . . . . . . . . . . . . 30 Functional description . . . . . . . . . . . . . . . . . . 37 I/O multiplexer control register. . . . . . . . . . . . 39 Power supply sequencing. . . . . . . . . . . . . . . . 40 Power on sequence . . . . . . . . . . . . . . . . . . . . 40 Power off sequence . . . . . . . . . . . . . . . . . . . . 41 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 41 Thermal characteristics. . . . . . . . . . . . . . . . . . 41 Static characteristics. . . . . . . . . . . . . . . . . . . . 42 Dynamic characteristics . . . . . . . . . . . . . . . . . 43 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral Controller Interface (PCI) timing . . 43 Main Memory Interface (MMI) timing . . . . . . . 45 General Purpose Input/Output (GPIO) timing. 45 Universal Asynchronous Receiver/Transmitter (UART) timing . . . . . . . . . . . . . . . . . . . . . . . . . 46 Synchronous Serial Interface (SSI) timing . . . 46 I2C-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . 47 IEEE 1394 Phy-Link interface . . . . . . . . . . . . . 47 I2S audio input & output timing. . . . . . . . . . . . 48 Sony Philips Digital Interface (SPDIF) timing . 49 Digital Video Output (DV Out) timing . . . . . . . 49 Digital Video Input (DV Input) timing. . . . . . . . 50 Transport Stream Output (TSO) timing. . . . . . 50 JTAG test contacts . . . . . . . . . . . . . . . . . . . . . 51 Delta compared to PNX8525 . . . . . . . . . . . . . . 51 Lifetime versus temperature. . . . . . . . . . . . . . 52 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 54 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 55 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 55 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 56 Package related soldering information . . . . . . 56 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 57 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 58 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 21 22 23 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 58 58 58 58
(c) Koninklijke Philips Electronics N.V. 2003. Printed in Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 6 October 2003 Document order number: 9397 750 11715

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